target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl()
Directly use tcg_constant_tl() for constant integer, this save a call to tcg_gen_movi_tl(), often saving a temp register. Most of the places found using the following Coccinelle spatch script: @@ identifier tmp; constant val; @@ * TCGv tmp = tcg_temp_new(); ... * tcg_gen_movi_tl(tmp, val); @@ identifier tmp; int val; @@ * TCGv tmp = tcg_temp_new(); ... * tcg_gen_movi_i64(tmp, val); Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241004202621.4321-2-philmd@linaro.org>
This commit is contained in:
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d0b24b7f50
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35845cf8fe
@ -1053,8 +1053,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
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tcg_gen_movi_tl(cpu_gpr[reg1], 0);
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}
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gen_set_label(lab_done);
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tcg_gen_movi_tl(lladdr, -1);
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tcg_gen_st_tl(lladdr, tcg_env, offsetof(CPUMIPSState, lladdr));
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tcg_gen_st_tl(tcg_constant_tl(-1), tcg_env, offsetof(CPUMIPSState, lladdr));
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}
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static void gen_adjust_sp(DisasContext *ctx, int u)
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@ -1544,7 +1543,6 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
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{
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int16_t imm;
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv v0_t = tcg_temp_new();
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gen_load_gpr(v0_t, v1);
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@ -1571,12 +1569,10 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
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check_dsp(ctx);
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switch (extract32(ctx->opcode, 12, 2)) {
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case NM_MTHLIP:
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tcg_gen_movi_tl(t0, v2 >> 3);
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gen_helper_mthlip(t0, v0_t, tcg_env);
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gen_helper_mthlip(tcg_constant_tl(v2 >> 3), v0_t, tcg_env);
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break;
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case NM_SHILOV:
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tcg_gen_movi_tl(t0, v2 >> 3);
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gen_helper_shilo(t0, v0_t, tcg_env);
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gen_helper_shilo(tcg_constant_tl(v2 >> 3), v0_t, tcg_env);
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break;
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default:
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gen_reserved_instruction(ctx);
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@ -1588,39 +1584,34 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
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imm = extract32(ctx->opcode, 14, 7);
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switch (extract32(ctx->opcode, 12, 2)) {
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case NM_RDDSP:
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tcg_gen_movi_tl(t0, imm);
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gen_helper_rddsp(t0, t0, tcg_env);
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gen_helper_rddsp(t0, tcg_constant_tl(imm), tcg_env);
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gen_store_gpr(t0, ret);
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break;
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case NM_WRDSP:
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gen_load_gpr(t0, ret);
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tcg_gen_movi_tl(t1, imm);
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gen_helper_wrdsp(t0, t1, tcg_env);
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gen_helper_wrdsp(t0, tcg_constant_tl(imm), tcg_env);
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break;
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case NM_EXTP:
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tcg_gen_movi_tl(t0, v2 >> 3);
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tcg_gen_movi_tl(t1, v1);
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gen_helper_extp(t0, t0, t1, tcg_env);
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gen_helper_extp(t0, tcg_constant_tl(v2 >> 3),
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tcg_constant_tl(v1), tcg_env);
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gen_store_gpr(t0, ret);
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break;
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case NM_EXTPDP:
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tcg_gen_movi_tl(t0, v2 >> 3);
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tcg_gen_movi_tl(t1, v1);
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gen_helper_extpdp(t0, t0, t1, tcg_env);
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gen_helper_extpdp(t0, tcg_constant_tl(v2 >> 3),
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tcg_constant_tl(v1), tcg_env);
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gen_store_gpr(t0, ret);
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break;
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}
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break;
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case NM_POOL32AXF_1_4:
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check_dsp(ctx);
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tcg_gen_movi_tl(t0, v2 >> 2);
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switch (extract32(ctx->opcode, 12, 1)) {
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case NM_SHLL_QB:
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gen_helper_shll_qb(t0, t0, v0_t, tcg_env);
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gen_helper_shll_qb(t0, tcg_constant_tl(v2 >> 2), v0_t, tcg_env);
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gen_store_gpr(t0, ret);
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break;
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case NM_SHRL_QB:
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gen_helper_shrl_qb(t0, t0, v0_t);
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gen_helper_shrl_qb(t0, tcg_constant_tl(v2 >> 2), v0_t);
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gen_store_gpr(t0, ret);
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break;
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}
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@ -1631,23 +1622,25 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
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break;
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case NM_POOL32AXF_1_7:
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check_dsp(ctx);
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tcg_gen_movi_tl(t0, v2 >> 3);
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tcg_gen_movi_tl(t1, v1);
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switch (extract32(ctx->opcode, 12, 2)) {
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case NM_EXTR_W:
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gen_helper_extr_w(t0, t0, t1, tcg_env);
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gen_helper_extr_w(t0, tcg_constant_tl(v2 >> 3),
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tcg_constant_tl(v1), tcg_env);
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gen_store_gpr(t0, ret);
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break;
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case NM_EXTR_R_W:
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gen_helper_extr_r_w(t0, t0, t1, tcg_env);
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gen_helper_extr_r_w(t0, tcg_constant_tl(v2 >> 3),
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tcg_constant_tl(v1), tcg_env);
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gen_store_gpr(t0, ret);
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break;
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case NM_EXTR_RS_W:
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gen_helper_extr_rs_w(t0, t0, t1, tcg_env);
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gen_helper_extr_rs_w(t0, tcg_constant_tl(v2 >> 3),
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tcg_constant_tl(v1), tcg_env);
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gen_store_gpr(t0, ret);
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break;
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case NM_EXTR_S_H:
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gen_helper_extr_s_h(t0, t0, t1, tcg_env);
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gen_helper_extr_s_h(t0, tcg_constant_tl(v2 >> 3),
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tcg_constant_tl(v1), tcg_env);
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gen_store_gpr(t0, ret);
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break;
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}
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@ -1849,8 +1842,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
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case NM_EXTRV_W:
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check_dsp(ctx);
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gen_load_gpr(v1_t, rs);
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tcg_gen_movi_tl(t0, rd >> 3);
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gen_helper_extr_w(t0, t0, v1_t, tcg_env);
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gen_helper_extr_w(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env);
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gen_store_gpr(t0, ret);
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break;
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}
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@ -1904,8 +1896,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
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break;
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case NM_EXTRV_R_W:
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check_dsp(ctx);
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tcg_gen_movi_tl(t0, rd >> 3);
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gen_helper_extr_r_w(t0, t0, v1_t, tcg_env);
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gen_helper_extr_r_w(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env);
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gen_store_gpr(t0, ret);
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break;
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default:
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@ -1924,8 +1915,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
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break;
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case NM_EXTPV:
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check_dsp(ctx);
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tcg_gen_movi_tl(t0, rd >> 3);
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gen_helper_extp(t0, t0, v1_t, tcg_env);
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gen_helper_extp(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env);
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gen_store_gpr(t0, ret);
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break;
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case NM_MSUB:
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@ -1948,8 +1938,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
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break;
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case NM_EXTRV_RS_W:
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check_dsp(ctx);
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tcg_gen_movi_tl(t0, rd >> 3);
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gen_helper_extr_rs_w(t0, t0, v1_t, tcg_env);
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gen_helper_extr_rs_w(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env);
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gen_store_gpr(t0, ret);
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break;
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}
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@ -1965,8 +1954,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
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break;
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case NM_EXTPDPV:
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check_dsp(ctx);
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tcg_gen_movi_tl(t0, rd >> 3);
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gen_helper_extpdp(t0, t0, v1_t, tcg_env);
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gen_helper_extpdp(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env);
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gen_store_gpr(t0, ret);
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break;
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case NM_MSUBU:
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@ -1991,8 +1979,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
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break;
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case NM_EXTRV_S_H:
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check_dsp(ctx);
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tcg_gen_movi_tl(t0, rd >> 3);
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gen_helper_extr_s_h(t0, t0, v1_t, tcg_env);
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gen_helper_extr_s_h(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env);
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gen_store_gpr(t0, ret);
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break;
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}
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@ -2150,24 +2137,22 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
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switch (opc) {
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case NM_SHRA_R_QB:
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check_dsp_r2(ctx);
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tcg_gen_movi_tl(t0, rd >> 2);
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switch (extract32(ctx->opcode, 12, 1)) {
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case 0:
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/* NM_SHRA_QB */
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gen_helper_shra_qb(t0, t0, rs_t);
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gen_helper_shra_qb(t0, tcg_constant_tl(rd >> 2), rs_t);
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gen_store_gpr(t0, rt);
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break;
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case 1:
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/* NM_SHRA_R_QB */
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gen_helper_shra_r_qb(t0, t0, rs_t);
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gen_helper_shra_r_qb(t0, tcg_constant_tl(rd >> 2), rs_t);
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gen_store_gpr(t0, rt);
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break;
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}
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break;
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case NM_SHRL_PH:
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check_dsp_r2(ctx);
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tcg_gen_movi_tl(t0, rd >> 1);
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gen_helper_shrl_ph(t0, t0, rs_t);
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gen_helper_shrl_ph(t0, tcg_constant_tl(rd >> 1), rs_t);
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gen_store_gpr(t0, rt);
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break;
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case NM_REPL_QB:
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@ -2181,8 +2166,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
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(uint32_t)imm << 8 |
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(uint32_t)imm;
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result = (int32_t)result;
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tcg_gen_movi_tl(t0, result);
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gen_store_gpr(t0, rt);
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gen_store_gpr(tcg_constant_tl(result), rt);
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}
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break;
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default:
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@ -2303,10 +2287,9 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
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{
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TCGCond cond = TCG_COND_ALWAYS;
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv timm = tcg_constant_tl(imm);
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gen_load_gpr(t0, rt);
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tcg_gen_movi_tl(t1, imm);
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ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
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/* Load needed operands and calculate btarget */
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@ -2335,7 +2318,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
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} else {
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tcg_gen_shri_tl(t0, t0, imm);
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tcg_gen_andi_tl(t0, t0, 1);
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tcg_gen_movi_tl(t1, 0);
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timm = tcg_constant_tl(0);
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if (opc == NM_BBEQZC) {
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cond = TCG_COND_EQ;
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} else {
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@ -2390,7 +2373,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
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/* Conditional compact branch */
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TCGLabel *fs = gen_new_label();
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tcg_gen_brcond_tl(tcg_invert_cond(cond), t0, t1, fs);
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tcg_gen_brcond_tl(tcg_invert_cond(cond), t0, timm, fs);
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gen_goto_tb(ctx, 1, ctx->btarget);
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gen_set_label(fs);
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@ -2404,7 +2387,6 @@ static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,
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int rt)
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{
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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/* load rs */
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gen_load_gpr(t0, rs);
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@ -2416,8 +2398,7 @@ static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,
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/* calculate btarget */
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tcg_gen_shli_tl(t0, t0, 1);
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tcg_gen_movi_tl(t1, ctx->base.pc_next + 4);
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gen_op_addr_add(ctx, btarget, t1, t0);
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gen_op_addr_add(ctx, btarget, tcg_constant_tl(ctx->base.pc_next + 4), t0);
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/* branch completion */
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clear_branch_hflags(ctx);
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@ -3444,13 +3425,10 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
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case NM_SHILO:
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check_dsp(ctx);
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{
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TCGv tv0 = tcg_temp_new();
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TCGv tv1 = tcg_temp_new();
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int16_t imm = extract32(ctx->opcode, 16, 7);
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tcg_gen_movi_tl(tv0, rd >> 3);
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tcg_gen_movi_tl(tv1, imm);
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gen_helper_shilo(tv0, tv1, tcg_env);
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gen_helper_shilo(tcg_constant_tl(rd >> 3),
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tcg_constant_tl(imm), tcg_env);
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}
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break;
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case NM_MULEQ_S_W_PHL:
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@ -3505,8 +3483,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
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break;
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case NM_SHRA_R_W:
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check_dsp(ctx);
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tcg_gen_movi_tl(t0, rd);
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gen_helper_shra_r_w(v1_t, t0, v1_t);
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gen_helper_shra_r_w(v1_t, tcg_constant_tl(rd), v1_t);
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gen_store_gpr(v1_t, rt);
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break;
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case NM_SHRA_R_PH:
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@ -3546,8 +3523,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
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break;
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case NM_SHLL_S_W:
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check_dsp(ctx);
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tcg_gen_movi_tl(t0, rd);
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gen_helper_shll_s_w(v1_t, t0, v1_t, tcg_env);
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gen_helper_shll_s_w(v1_t, tcg_constant_tl(rd), v1_t, tcg_env);
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gen_store_gpr(v1_t, rt);
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break;
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case NM_REPL_PH:
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@ -3728,14 +3704,11 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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case NM_LWPC48:
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check_nms(ctx);
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if (rt != 0) {
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TCGv t0;
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t0 = tcg_temp_new();
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target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
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addr_off);
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tcg_gen_movi_tl(t0, addr);
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tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx,
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tcg_gen_qemu_ld_tl(cpu_gpr[rt], tcg_constant_tl(addr),
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ctx->mem_idx,
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mo_endian(ctx) | MO_SL
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| ctx->default_tcg_memop_mask);
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}
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@ -3743,17 +3716,15 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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case NM_SWPC48:
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check_nms(ctx);
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{
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TCGv t0, t1;
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t0 = tcg_temp_new();
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TCGv t1;
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t1 = tcg_temp_new();
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target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
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addr_off);
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tcg_gen_movi_tl(t0, addr);
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gen_load_gpr(t1, rt);
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
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tcg_gen_qemu_st_tl(t1, tcg_constant_tl(addr), ctx->mem_idx,
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mo_endian(ctx) | MO_UL
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| ctx->default_tcg_memop_mask);
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}
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@ -2252,8 +2252,7 @@ static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
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/* compare the address against that of the preceding LL */
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gen_base_offset_addr(ctx, addr, base, offset);
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tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
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tcg_gen_movi_tl(t0, 0);
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gen_store_gpr(t0, rt);
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gen_store_gpr(tcg_constant_tl(0), rt);
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tcg_gen_br(done);
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gen_set_label(l1);
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@ -3059,8 +3058,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
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tcg_gen_and_tl(t2, t2, t3);
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tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
|
||||
tcg_gen_or_tl(t2, t2, t3);
|
||||
tcg_gen_movi_tl(t3, 0);
|
||||
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
|
||||
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
|
||||
tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
|
||||
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
|
||||
}
|
||||
@ -3076,30 +3074,27 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
|
||||
tcg_gen_and_tl(t2, t2, t3);
|
||||
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
|
||||
tcg_gen_or_tl(t2, t2, t3);
|
||||
tcg_gen_movi_tl(t3, 0);
|
||||
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
|
||||
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
|
||||
tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
|
||||
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
|
||||
}
|
||||
break;
|
||||
case R6_OPC_DIVU:
|
||||
{
|
||||
TCGv t2 = tcg_constant_tl(0);
|
||||
TCGv t3 = tcg_constant_tl(1);
|
||||
tcg_gen_ext32u_tl(t0, t0);
|
||||
tcg_gen_ext32u_tl(t1, t1);
|
||||
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
|
||||
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
|
||||
tcg_constant_tl(0), tcg_constant_tl(1), t1);
|
||||
tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
|
||||
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
|
||||
}
|
||||
break;
|
||||
case R6_OPC_MODU:
|
||||
{
|
||||
TCGv t2 = tcg_constant_tl(0);
|
||||
TCGv t3 = tcg_constant_tl(1);
|
||||
tcg_gen_ext32u_tl(t0, t0);
|
||||
tcg_gen_ext32u_tl(t1, t1);
|
||||
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
|
||||
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
|
||||
tcg_constant_tl(0), tcg_constant_tl(1), t1);
|
||||
tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
|
||||
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
|
||||
}
|
||||
@ -3154,8 +3149,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
|
||||
tcg_gen_and_tl(t2, t2, t3);
|
||||
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
|
||||
tcg_gen_or_tl(t2, t2, t3);
|
||||
tcg_gen_movi_tl(t3, 0);
|
||||
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
|
||||
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
|
||||
tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
|
||||
}
|
||||
break;
|
||||
@ -3168,24 +3162,21 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
|
||||
tcg_gen_and_tl(t2, t2, t3);
|
||||
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
|
||||
tcg_gen_or_tl(t2, t2, t3);
|
||||
tcg_gen_movi_tl(t3, 0);
|
||||
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
|
||||
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
|
||||
tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
|
||||
}
|
||||
break;
|
||||
case R6_OPC_DDIVU:
|
||||
{
|
||||
TCGv t2 = tcg_constant_tl(0);
|
||||
TCGv t3 = tcg_constant_tl(1);
|
||||
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
|
||||
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
|
||||
tcg_constant_tl(0), tcg_constant_tl(1), t1);
|
||||
tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
|
||||
}
|
||||
break;
|
||||
case R6_OPC_DMODU:
|
||||
{
|
||||
TCGv t2 = tcg_constant_tl(0);
|
||||
TCGv t3 = tcg_constant_tl(1);
|
||||
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
|
||||
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
|
||||
tcg_constant_tl(0), tcg_constant_tl(1), t1);
|
||||
tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
|
||||
}
|
||||
break;
|
||||
@ -3238,8 +3229,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
|
||||
tcg_gen_and_tl(t2, t2, t3);
|
||||
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
|
||||
tcg_gen_or_tl(t2, t2, t3);
|
||||
tcg_gen_movi_tl(t3, 0);
|
||||
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
|
||||
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
|
||||
tcg_gen_div_tl(cpu_LO[1], t0, t1);
|
||||
tcg_gen_rem_tl(cpu_HI[1], t0, t1);
|
||||
tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
|
||||
@ -3294,8 +3284,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
|
||||
tcg_gen_and_tl(t2, t2, t3);
|
||||
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
|
||||
tcg_gen_or_tl(t2, t2, t3);
|
||||
tcg_gen_movi_tl(t3, 0);
|
||||
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
|
||||
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
|
||||
tcg_gen_div_tl(cpu_LO[acc], t0, t1);
|
||||
tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
|
||||
tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
|
||||
@ -3347,17 +3336,15 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
|
||||
tcg_gen_and_tl(t2, t2, t3);
|
||||
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
|
||||
tcg_gen_or_tl(t2, t2, t3);
|
||||
tcg_gen_movi_tl(t3, 0);
|
||||
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
|
||||
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
|
||||
tcg_gen_div_tl(cpu_LO[acc], t0, t1);
|
||||
tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
|
||||
}
|
||||
break;
|
||||
case OPC_DDIVU:
|
||||
{
|
||||
TCGv t2 = tcg_constant_tl(0);
|
||||
TCGv t3 = tcg_constant_tl(1);
|
||||
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
|
||||
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
|
||||
tcg_constant_tl(0), tcg_constant_tl(1), t1);
|
||||
tcg_gen_divu_i64(cpu_LO[acc], t0, t1);
|
||||
tcg_gen_remu_i64(cpu_HI[acc], t0, t1);
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user