Mostly bugfixes and small improvements; and the gdb target.xml
patch. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJWqfU2AAoJEN7Pa5PG8C+vxhQQAIYOS/ipBececOJv/nMGBDVH nXZs7T/QPV0b0cYeqb4r0g+Dbg4bywdbF7/bdULJtOsygK7Y9U4FlL+S1wL7D3x1 YcqrXCwX8xSqqd51wzYshIwbRO/22G/7pyGa2jSvHTiPJlLJUsPF09z5otSZ3p8g 4JW2Xmfx3MF20IBMQgazB4dd/Lz6EKy8MJbqrcQUc9+mpsstL3I4L5AUF59jlARY 0e73OYbBRUZaHmGpI24uRO2OLhYWKwmVkaUo8FfZB3W94k0PXcsQ/Kg8UJbqlwY/ PTYDhhSm6JycLyLp/0MnlHuyHiKtCnQyl+4O27lWOiQWUzKELiereO9MFlUwRg5L N6f4IwpDqTGU2tmj1ujLbzI2kaVEuVu++gIaBe+LL8BYNtcf25/3eVQ71WL1ioQV YRooC3eWAVQtLgjM04+F5fiMgxXSklowb29ONwm/M6dfYl0mXhKoPuE9rkRSUKfZ jPsK7HM4hHM2nHY+JQZnoAWV0DMBT0d4Ehe1pDrQ2lu5XDMNYip3buW/VEzqZTzF Buk2tIhJFA6EriU2OAj+6+ENqia/7PMWpPry/0wi2Tmgt1ksu8DFyfati4PP31Or A/jYo10mzn4cZtrgI9kavg1Ij5c8Ij9h3oNg2pVDZfXKQmIxIqxgPq8/puwK3ywU DOBAAglu8nLgHv+EJTNz =lF/D -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160128' into staging Mostly bugfixes and small improvements; and the gdb target.xml patch. # gpg: Signature made Thu 28 Jan 2016 11:02:14 GMT using RSA key ID C6F02FAF # gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" * remotes/cohuck/tags/s390x-20160128: s390x: s390_cpu_get_phys_page_debug has to return -1 gdb: provide the name of the architecture in the target.xml s390x/css: fix control flags during csch watchdog/diag288: don't reset for action=none|debug|pause watchdog: introduction of get_watchdog_action s390x: fix generation of event information crw s390x/ioinst: set type and len for SEI response s390x/sclp: add device to the sysbus in sclp_realize s390x/machine: make addon register fields static s390x/skeys: Fix instance and class size Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
357e81c7e8
21
gdbstub.c
21
gdbstub.c
@ -540,13 +540,20 @@ static const char *get_feature_xml(const char *p, const char **newp,
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GDBRegisterState *r;
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CPUState *cpu = first_cpu;
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snprintf(target_xml, sizeof(target_xml),
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"<?xml version=\"1.0\"?>"
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"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
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"<target>"
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"<xi:include href=\"%s\"/>",
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cc->gdb_core_xml_file);
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pstrcat(target_xml, sizeof(target_xml),
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"<?xml version=\"1.0\"?>"
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"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
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"<target>");
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if (cc->gdb_arch_name) {
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gchar *arch = cc->gdb_arch_name(cpu);
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pstrcat(target_xml, sizeof(target_xml), "<architecture>");
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pstrcat(target_xml, sizeof(target_xml), arch);
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pstrcat(target_xml, sizeof(target_xml), "</architecture>");
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g_free(arch);
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}
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pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\"");
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pstrcat(target_xml, sizeof(target_xml), cc->gdb_core_xml_file);
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pstrcat(target_xml, sizeof(target_xml), "\"/>");
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for (r = cpu->gdb_regs; r; r = r->next) {
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pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\"");
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pstrcat(target_xml, sizeof(target_xml), r->xml);
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@ -49,6 +49,7 @@ typedef struct IoAdapter {
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typedef struct ChannelSubSys {
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QTAILQ_HEAD(, CrwContainer) pending_crws;
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bool sei_pending;
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bool do_crw_mchk;
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bool crws_lost;
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uint8_t max_cssid;
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@ -701,7 +702,7 @@ int css_do_csch(SubchDev *sch)
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/* Trigger the clear function. */
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s->ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL);
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s->ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_FCTL_CLEAR_FUNC;
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s->ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_ACTL_CLEAR_PEND;
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do_subchannel_work(sch, NULL);
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ret = 0;
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@ -1359,7 +1360,15 @@ void css_generate_chp_crws(uint8_t cssid, uint8_t chpid)
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void css_generate_css_crws(uint8_t cssid)
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{
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css_queue_crw(CRW_RSC_CSS, 0, 0, cssid);
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if (!channel_subsys->sei_pending) {
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css_queue_crw(CRW_RSC_CSS, 0, 0, cssid);
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}
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channel_subsys->sei_pending = true;
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}
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void css_clear_sei_pending(void)
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{
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channel_subsys->sei_pending = false;
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}
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int css_enable_mcsse(void)
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@ -1509,6 +1518,7 @@ static void css_init(void)
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{
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channel_subsys = g_malloc0(sizeof(*channel_subsys));
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QTAILQ_INIT(&channel_subsys->pending_crws);
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channel_subsys->sei_pending = false;
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channel_subsys->do_crw_mchk = true;
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channel_subsys->crws_lost = false;
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channel_subsys->chnmon_active = false;
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@ -1561,6 +1571,7 @@ void css_reset(void)
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QTAILQ_REMOVE(&channel_subsys->pending_crws, crw_cont, sibling);
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g_free(crw_cont);
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}
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channel_subsys->sei_pending = false;
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channel_subsys->do_crw_mchk = true;
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channel_subsys->crws_lost = false;
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@ -103,6 +103,7 @@ void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
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int hotplugged, int add);
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void css_generate_chp_crws(uint8_t cssid, uint8_t chpid);
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void css_generate_css_crws(uint8_t cssid);
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void css_clear_sei_pending(void);
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void css_adapter_interrupt(uint8_t isc);
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#define CSS_IO_ADAPTER_VIRTIO 1
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@ -237,7 +237,7 @@ static const TypeInfo qemu_s390_skeys_info = {
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.instance_init = qemu_s390_skeys_init,
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.instance_size = sizeof(QEMUS390SKeysState),
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.class_init = qemu_s390_skeys_class_init,
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.instance_size = sizeof(S390SKeysClass),
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.class_size = sizeof(S390SKeysClass),
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};
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static void s390_storage_keys_save(QEMUFile *f, void *opaque)
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@ -465,6 +465,12 @@ static void sclp_realize(DeviceState *dev, Error **errp)
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if (err) {
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goto out;
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}
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/*
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* qdev_device_add searches the sysbus for TYPE_SCLP_EVENTS_BUS. As long
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* as we can't find a fitting bus via the qom tree, we have to add the
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* event facility to the sysbus, so e.g. a sclp console can be created.
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*/
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qdev_set_parent_bus(DEVICE(sclp->event_facility), sysbus_get_default());
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ret = s390_set_memory_limit(machine->maxram_size, &hw_limit);
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if (ret == -E2BIG) {
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@ -533,8 +539,6 @@ static void sclp_init(Object *obj)
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new = object_new(TYPE_SCLP_EVENT_FACILITY);
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object_property_add_child(obj, TYPE_SCLP_EVENT_FACILITY, new, NULL);
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/* qdev_device_add searches the sysbus for TYPE_SCLP_EVENTS_BUS */
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qdev_set_parent_bus(DEVICE(new), sysbus_get_default());
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object_unref(new);
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sclp->event_facility = EVENT_FACILITY(new);
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@ -29,15 +29,6 @@
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#include "qapi-event.h"
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#include "hw/nmi.h"
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/* Possible values for action parameter. */
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#define WDT_RESET 1 /* Hard reset. */
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#define WDT_SHUTDOWN 2 /* Shutdown. */
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#define WDT_POWEROFF 3 /* Quit. */
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#define WDT_PAUSE 4 /* Pause. */
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#define WDT_DEBUG 5 /* Prints a message and continues running. */
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#define WDT_NONE 6 /* Do nothing. */
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#define WDT_NMI 7 /* Inject nmi into the guest */
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static int watchdog_action = WDT_RESET;
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static QLIST_HEAD(watchdog_list, WatchdogTimerModel) watchdog_list;
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@ -105,6 +96,11 @@ int select_watchdog_action(const char *p)
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return 0;
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}
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int get_watchdog_action(void)
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{
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return watchdog_action;
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}
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/* This actually performs the "action" once a watchdog has expired,
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* ie. reboot, shutdown, exit, etc.
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*/
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@ -51,6 +51,13 @@ static void diag288_timer_expired(void *dev)
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{
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qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n");
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watchdog_perform_action();
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/* Reset the watchdog only if the guest was notified about expiry. */
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switch (get_watchdog_action()) {
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case WDT_DEBUG:
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case WDT_NONE:
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case WDT_PAUSE:
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return;
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}
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wdt_diag288_reset(dev);
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}
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@ -120,6 +120,8 @@ struct TranslationBlock;
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* @gdb_core_xml_file: File name for core registers GDB XML description.
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* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
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* before the insn which triggers a watchpoint rather than after it.
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* @gdb_arch_name: Optional callback that returns the architecture name known
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* to GDB. The caller must free the returned string with g_free.
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* @cpu_exec_enter: Callback for cpu_exec preparation.
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* @cpu_exec_exit: Callback for cpu_exec cleanup.
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* @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
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@ -177,6 +179,7 @@ typedef struct CPUClass {
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const struct VMStateDescription *vmsd;
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int gdb_num_core_regs;
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const char *gdb_core_xml_file;
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gchar * (*gdb_arch_name)(CPUState *cpu);
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bool gdb_stop_before_watchpoint;
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void (*cpu_exec_enter)(CPUState *cpu);
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@ -24,6 +24,15 @@
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#include "qemu/queue.h"
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/* Possible values for action parameter. */
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#define WDT_RESET 1 /* Hard reset. */
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#define WDT_SHUTDOWN 2 /* Shutdown. */
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#define WDT_POWEROFF 3 /* Quit. */
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#define WDT_PAUSE 4 /* Pause. */
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#define WDT_DEBUG 5 /* Prints a message and continues running. */
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#define WDT_NONE 6 /* Do nothing. */
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#define WDT_NMI 7 /* Inject nmi into the guest. */
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struct WatchdogTimerModel {
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QLIST_ENTRY(WatchdogTimerModel) entry;
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@ -37,6 +46,7 @@ typedef struct WatchdogTimerModel WatchdogTimerModel;
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/* in hw/watchdog.c */
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int select_watchdog(const char *p);
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int select_watchdog_action(const char *action);
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int get_watchdog_action(void);
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void watchdog_add_model(WatchdogTimerModel *model);
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void watchdog_perform_action(void);
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@ -1426,6 +1426,17 @@ static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
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}
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#endif
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static gchar *arm_gdb_arch_name(CPUState *cs)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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return g_strdup("iwmmxt");
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}
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return g_strdup("arm");
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}
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static void arm_cpu_class_init(ObjectClass *oc, void *data)
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{
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ARMCPUClass *acc = ARM_CPU_CLASS(oc);
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@ -1460,6 +1471,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
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#endif
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cc->gdb_num_core_regs = 26;
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cc->gdb_core_xml_file = "arm-core.xml";
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cc->gdb_arch_name = arm_gdb_arch_name;
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cc->gdb_stop_before_watchpoint = true;
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cc->debug_excp_handler = arm_debug_excp_handler;
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@ -287,6 +287,11 @@ static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
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}
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}
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static gchar *aarch64_gdb_arch_name(CPUState *cs)
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{
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return g_strdup("aarch64");
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}
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static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(oc);
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@ -297,6 +302,7 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
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cc->gdb_write_register = aarch64_cpu_gdb_write_register;
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cc->gdb_num_core_regs = 34;
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cc->gdb_core_xml_file = "aarch64-core.xml";
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cc->gdb_arch_name = aarch64_gdb_arch_name;
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}
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static void aarch64_cpu_register(const ARMCPUInfo *info)
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@ -9681,6 +9681,15 @@ static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
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return pcc->pvr == pvr;
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}
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static gchar *ppc_gdb_arch_name(CPUState *cs)
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{
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#if defined(TARGET_PPC64)
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return g_strdup("powerpc:common64");
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#else
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return g_strdup("powerpc:common");
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#endif
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}
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static void ppc_cpu_class_init(ObjectClass *oc, void *data)
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{
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PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
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@ -9724,6 +9733,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
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cc->gdb_num_core_regs = 71 + 32;
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#endif
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cc->gdb_arch_name = ppc_gdb_arch_name;
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#if defined(TARGET_PPC64)
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cc->gdb_core_xml_file = "power64-core.xml";
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#else
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@ -325,6 +325,11 @@ unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
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}
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#endif
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static gchar *s390_gdb_arch_name(CPUState *cs)
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{
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return g_strdup("s390:64-bit");
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}
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static void s390_cpu_class_init(ObjectClass *oc, void *data)
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{
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S390CPUClass *scc = S390_CPU_CLASS(oc);
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@ -360,6 +365,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
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cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
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cc->gdb_core_xml_file = "s390x-core64.xml";
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cc->gdb_arch_name = s390_gdb_arch_name;
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/*
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* Reason: s390_cpu_initfn() calls cpu_exec_init(), which saves
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@ -162,8 +162,9 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
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vaddr &= 0x7fffffff;
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}
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mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false);
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if (mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false)) {
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return -1;
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}
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return raddr;
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}
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@ -614,9 +614,11 @@ static void ioinst_handle_chsc_sei(ChscReq *req, ChscResp *res)
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(*res_flags) |= 0x80;
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} else {
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(*res_flags) &= ~0x80;
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css_clear_sei_pending();
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}
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} else {
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res->code = cpu_to_be16(0x0004);
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res->code = cpu_to_be16(0x0005);
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res->len = cpu_to_be16(CHSC_MIN_RESP_LEN);
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}
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}
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@ -48,7 +48,7 @@ static inline bool fpu_needed(void *opaque)
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return true;
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}
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const VMStateDescription vmstate_fpu = {
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static const VMStateDescription vmstate_fpu = {
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.name = "cpu/fpu",
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.version_id = 1,
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.minimum_version_id = 1,
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@ -75,7 +75,7 @@ const VMStateDescription vmstate_fpu = {
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}
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};
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const VMStateDescription vmstate_vregs = {
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static const VMStateDescription vmstate_vregs = {
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.name = "cpu/vregs",
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.version_id = 1,
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.minimum_version_id = 1,
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