target/riscv: Enable PC-relative translation
Add a base pc_save for PC-relative translation(CF_PCREL). Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb. Use gen_pc_plus_diff to get the pc-relative address. Enable CF_PCREL in System mode. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230526072124.298466-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -721,6 +721,7 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
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static void riscv_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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{
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if (!(tb_cflags(tb) & CF_PCREL)) {
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
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@ -732,6 +733,7 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
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} else {
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env->pc = tb->pc;
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}
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}
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}
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static bool riscv_cpu_has_work(CPUState *cs)
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@ -756,11 +758,18 @@ static void riscv_restore_state_to_opc(CPUState *cs,
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
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target_ulong pc;
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if (tb_cflags(tb) & CF_PCREL) {
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pc = (env->pc & TARGET_PAGE_MASK) | data[0];
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} else {
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pc = data[0];
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}
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if (xl == MXL_RV32) {
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env->pc = (int32_t)data[0];
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env->pc = (int32_t)pc;
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} else {
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env->pc = data[0];
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env->pc = pc;
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}
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env->bins = data[1];
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}
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@ -1343,6 +1352,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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}
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#ifndef CONFIG_USER_ONLY
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cs->tcg_cflags |= CF_PCREL;
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if (cpu->cfg.ext_sstc) {
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riscv_timer_init(cpu);
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}
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@ -38,7 +38,9 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
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static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
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{
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gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
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TCGv target_pc = dest_gpr(ctx, a->rd);
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gen_pc_plus_diff(target_pc, ctx, a->imm);
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gen_set_gpr(ctx, a->rd, target_pc);
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return true;
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}
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@ -52,6 +54,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
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{
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TCGLabel *misaligned = NULL;
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TCGv target_pc = tcg_temp_new();
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TCGv succ_pc = dest_gpr(ctx, a->rd);
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tcg_gen_addi_tl(target_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
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tcg_gen_andi_tl(target_pc, target_pc, (target_ulong)-2);
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@ -68,7 +71,9 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
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tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
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}
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gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
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gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
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gen_set_gpr(ctx, a->rd, succ_pc);
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tcg_gen_mov_tl(cpu_pc, target_pc);
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lookup_and_goto_ptr(ctx);
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@ -158,6 +163,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
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TCGLabel *l = gen_new_label();
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TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
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TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
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target_ulong orig_pc_save = ctx->pc_save;
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if (get_xl(ctx) == MXL_RV128) {
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TCGv src1h = get_gprh(ctx, a->rs1);
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@ -171,6 +177,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
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tcg_gen_brcond_tl(cond, src1, src2, l);
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}
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gen_goto_tb(ctx, 1, ctx->cur_insn_len);
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ctx->pc_save = orig_pc_save;
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gen_set_label(l); /* branch taken */
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@ -183,6 +190,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
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} else {
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gen_goto_tb(ctx, 0, a->imm);
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}
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ctx->pc_save = -1;
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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@ -302,7 +302,9 @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a)
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/* c.jt vs c.jalt depends on the index. */
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if (a->index >= 32) {
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gen_set_gpri(ctx, xRA, ctx->pc_succ_insn);
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TCGv succ_pc = dest_gpr(ctx, xRA);
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gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
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gen_set_gpr(ctx, xRA, succ_pc);
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}
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tcg_gen_lookup_and_goto_ptr();
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@ -62,6 +62,7 @@ typedef struct DisasContext {
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/* pc_succ_insn points to the instruction following base.pc_next */
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target_ulong pc_succ_insn;
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target_ulong cur_insn_len;
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target_ulong pc_save;
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target_ulong priv_ver;
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RISCVMXL misa_mxl_max;
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RISCVMXL xl;
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@ -230,15 +231,24 @@ static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
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{
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target_ulong dest = ctx->base.pc_next + diff;
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assert(ctx->pc_save != -1);
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if (tb_cflags(ctx->base.tb) & CF_PCREL) {
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tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save);
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if (get_xl(ctx) == MXL_RV32) {
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tcg_gen_ext32s_tl(target, target);
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}
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} else {
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if (get_xl(ctx) == MXL_RV32) {
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dest = (int32_t)dest;
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}
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tcg_gen_movi_tl(target, dest);
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}
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}
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static void gen_update_pc(DisasContext *ctx, target_long diff)
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{
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gen_pc_plus_diff(cpu_pc, ctx, diff);
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ctx->pc_save = ctx->base.pc_next + diff;
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}
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static void generate_exception(DisasContext *ctx, int excp)
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@ -294,8 +304,21 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
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* direct block chain benefits will be small.
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*/
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if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
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/*
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* For pcrel, the pc must always be up-to-date on entry to
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* the linked TB, so that it can use simple additions for all
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* further adjustments. For !pcrel, the linked TB is compiled
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* to know its full virtual address, so we can delay the
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* update to pc to the unlinked path. A long chain of links
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* can thus avoid many updates to the PC.
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*/
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if (tb_cflags(ctx->base.tb) & CF_PCREL) {
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gen_update_pc(ctx, diff);
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tcg_gen_goto_tb(n);
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} else {
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tcg_gen_goto_tb(n);
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gen_update_pc(ctx, diff);
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}
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tcg_gen_exit_tb(ctx->base.tb, n);
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} else {
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gen_update_pc(ctx, diff);
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@ -549,6 +572,8 @@ static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
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static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
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{
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TCGv succ_pc = dest_gpr(ctx, rd);
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/* check misaligned: */
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if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
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if ((imm & 0x3) != 0) {
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@ -559,7 +584,9 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
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}
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}
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gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
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gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len);
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gen_set_gpr(ctx, rd, succ_pc);
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gen_goto_tb(ctx, 0, imm); /* must use this for safety */
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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@ -1157,6 +1184,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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RISCVCPU *cpu = RISCV_CPU(cs);
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uint32_t tb_flags = ctx->base.tb->flags;
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ctx->pc_save = ctx->base.pc_first;
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ctx->pc_succ_insn = ctx->base.pc_first;
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ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
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ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
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@ -1192,8 +1220,13 @@ static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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target_ulong pc_next = ctx->base.pc_next;
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tcg_gen_insn_start(ctx->base.pc_next, 0);
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if (tb_cflags(dcbase->tb) & CF_PCREL) {
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pc_next &= ~TARGET_PAGE_MASK;
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}
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tcg_gen_insn_start(pc_next, 0);
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ctx->insn_start = tcg_last_op();
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}
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