Static'ify some functions, and use standard inline in translate.c.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4813 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -757,7 +757,7 @@ FOP_CONDS(abs, ps)
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/* Tests */
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#define OP_COND(name, cond) \
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void glue(gen_op_, name) (TCGv t0, TCGv t1) \
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static inline void glue(gen_op_, name) (TCGv t0, TCGv t1) \
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{ \
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int l1 = gen_new_label(); \
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int l2 = gen_new_label(); \
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@ -778,7 +778,7 @@ OP_COND(ltu, TCG_COND_LTU);
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#undef OP_COND
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#define OP_CONDI(name, cond) \
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void glue(gen_op_, name) (TCGv t, target_ulong val) \
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static inline void glue(gen_op_, name) (TCGv t, target_ulong val) \
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{ \
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int l1 = gen_new_label(); \
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int l2 = gen_new_label(); \
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@ -795,7 +795,7 @@ OP_CONDI(ltiu, TCG_COND_LTU);
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#undef OP_CONDI
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#define OP_CONDZ(name, cond) \
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void glue(gen_op_, name) (TCGv t) \
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static inline void glue(gen_op_, name) (TCGv t) \
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{ \
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int l1 = gen_new_label(); \
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int l2 = gen_new_label(); \
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@ -822,7 +822,7 @@ static inline void gen_save_pc(target_ulong pc)
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tcg_temp_free(r_tmp);
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}
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static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
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static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
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{
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#if defined MIPS_DEBUG_DISAS
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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@ -853,7 +853,7 @@ static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
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}
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}
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static always_inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
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static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
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{
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ctx->saved_hflags = ctx->hflags;
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switch (ctx->hflags & MIPS_HFLAG_BMASK) {
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@ -867,7 +867,7 @@ static always_inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
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}
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}
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static always_inline void
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static inline void
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generate_exception_err (DisasContext *ctx, int excp, int err)
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{
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save_cpu_state(ctx, 1);
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@ -876,7 +876,7 @@ generate_exception_err (DisasContext *ctx, int excp, int err)
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tcg_gen_exit_tb(0);
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}
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static always_inline void
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static inline void
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generate_exception (DisasContext *ctx, int excp)
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{
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save_cpu_state(ctx, 1);
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@ -911,13 +911,13 @@ static inline void gen_op_addr_add (TCGv t0, TCGv t1)
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#endif
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}
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static always_inline void check_cp0_enabled(DisasContext *ctx)
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static inline void check_cp0_enabled(DisasContext *ctx)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
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generate_exception_err(ctx, EXCP_CpU, 1);
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}
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static always_inline void check_cp1_enabled(DisasContext *ctx)
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static inline void check_cp1_enabled(DisasContext *ctx)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
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generate_exception_err(ctx, EXCP_CpU, 1);
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@ -927,7 +927,7 @@ static always_inline void check_cp1_enabled(DisasContext *ctx)
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This is associated with the nabla symbol in the MIPS32 and MIPS64
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opcode tables. */
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static always_inline void check_cop1x(DisasContext *ctx)
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static inline void check_cop1x(DisasContext *ctx)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))
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generate_exception(ctx, EXCP_RI);
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@ -936,7 +936,7 @@ static always_inline void check_cop1x(DisasContext *ctx)
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/* Verify that the processor is running with 64-bit floating-point
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operations enabled. */
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static always_inline void check_cp1_64bitmode(DisasContext *ctx)
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static inline void check_cp1_64bitmode(DisasContext *ctx)
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{
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if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))
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generate_exception(ctx, EXCP_RI);
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@ -953,7 +953,7 @@ static always_inline void check_cp1_64bitmode(DisasContext *ctx)
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* Multiple 64 bit wide registers can be checked by calling
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* gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
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*/
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void check_cp1_registers(DisasContext *ctx, int regs)
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static inline void check_cp1_registers(DisasContext *ctx, int regs)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
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generate_exception(ctx, EXCP_RI);
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@ -961,7 +961,7 @@ void check_cp1_registers(DisasContext *ctx, int regs)
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/* This code generates a "reserved instruction" exception if the
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CPU does not support the instruction set corresponding to flags. */
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static always_inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
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static inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
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{
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if (unlikely(!(env->insn_flags & flags)))
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generate_exception(ctx, EXCP_RI);
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@ -969,7 +969,7 @@ static always_inline void check_insn(CPUState *env, DisasContext *ctx, int flags
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/* This code generates a "reserved instruction" exception if 64-bit
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instructions are not enabled. */
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static always_inline void check_mips_64(DisasContext *ctx)
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static inline void check_mips_64(DisasContext *ctx)
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{
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
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generate_exception(ctx, EXCP_RI);
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@ -977,7 +977,7 @@ static always_inline void check_mips_64(DisasContext *ctx)
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/* load/store instructions. */
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#define OP_LD(insn,fname) \
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void inline op_ldst_##insn(TCGv t0, DisasContext *ctx) \
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static inline void op_ldst_##insn(TCGv t0, DisasContext *ctx) \
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{ \
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tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
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}
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@ -993,7 +993,7 @@ OP_LD(ld,ld64);
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#undef OP_LD
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#define OP_ST(insn,fname) \
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void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
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static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
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{ \
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tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
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}
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@ -1006,7 +1006,7 @@ OP_ST(sd,st64);
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#undef OP_ST
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#define OP_LD_ATOMIC(insn,fname) \
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void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
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static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
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{ \
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tcg_gen_mov_tl(t1, t0); \
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tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
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@ -1019,7 +1019,7 @@ OP_LD_ATOMIC(lld,ld64);
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#undef OP_LD_ATOMIC
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#define OP_ST_ATOMIC(insn,fname,almask) \
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void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
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static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
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{ \
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TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL); \
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int l1 = gen_new_label(); \
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@ -2459,7 +2459,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
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tcg_temp_free(t1);
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}
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static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
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static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
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{
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TranslationBlock *tb;
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tb = ctx->tb;
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@ -7808,7 +7808,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
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}
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}
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static always_inline int
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static inline int
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gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
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int search_pc)
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{
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