target-i386: Use movcond to implement rotate flags.
With this being all straight-line code, it can get deleted when the cc variables die. Signed-off-by: Richard Henderson <rth@twiddle.net>
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Richard Henderson
parent
a41f62f592
commit
34d80a55ff
@ -1698,167 +1698,172 @@ static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
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tcg_gen_shri_tl(ret, arg1, -arg2);
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}
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static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
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int is_right)
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static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, int is_right)
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{
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target_ulong mask;
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int label1, label2, data_bits;
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TCGv t0, t1, t2, a0;
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/* XXX: inefficient, but we must use local temps */
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t0 = tcg_temp_local_new();
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t1 = tcg_temp_local_new();
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t2 = tcg_temp_local_new();
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a0 = tcg_temp_local_new();
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if (ot == OT_QUAD)
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mask = 0x3f;
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else
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mask = 0x1f;
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target_ulong mask = (ot == OT_QUAD ? 0x3f : 0x1f);
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TCGv_i32 t0, t1;
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/* load */
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if (op1 == OR_TMP0) {
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tcg_gen_mov_tl(a0, cpu_A0);
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gen_op_ld_v(ot + s->mem_index, t0, a0);
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gen_op_ld_T0_A0(ot + s->mem_index);
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} else {
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gen_op_mov_v_reg(ot, t0, op1);
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gen_op_mov_TN_reg(ot, 0, op1);
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}
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tcg_gen_mov_tl(t1, cpu_T[1]);
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tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
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tcg_gen_andi_tl(t1, t1, mask);
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/* Must test zero case to avoid using undefined behaviour in TCG
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shifts. */
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label1 = gen_new_label();
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tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
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if (ot <= OT_WORD)
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tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
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else
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tcg_gen_mov_tl(cpu_tmp0, t1);
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gen_extu(ot, t0);
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tcg_gen_mov_tl(t2, t0);
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data_bits = 8 << ot;
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/* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
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fix TCG definition) */
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if (is_right) {
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tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
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tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
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tcg_gen_shl_tl(t0, t0, cpu_tmp0);
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} else {
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tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
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tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
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tcg_gen_shr_tl(t0, t0, cpu_tmp0);
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switch (ot) {
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case OT_BYTE:
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/* Replicate the 8-bit input so that a 32-bit rotate works. */
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tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
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tcg_gen_muli_tl(cpu_T[0], cpu_T[0], 0x01010101);
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goto do_long;
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case OT_WORD:
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/* Replicate the 16-bit input so that a 32-bit rotate works. */
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tcg_gen_deposit_tl(cpu_T[0], cpu_T[0], cpu_T[0], 16, 16);
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goto do_long;
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do_long:
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#ifdef TARGET_X86_64
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case OT_LONG:
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tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
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tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
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if (is_right) {
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tcg_gen_rotr_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32);
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} else {
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tcg_gen_rotl_i32(cpu_tmp2_i32, cpu_tmp2_i32, cpu_tmp3_i32);
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}
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tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
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break;
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#endif
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default:
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if (is_right) {
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tcg_gen_rotr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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} else {
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tcg_gen_rotl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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}
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break;
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}
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tcg_gen_or_tl(t0, t0, cpu_tmp4);
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gen_set_label(label1);
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/* store */
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if (op1 == OR_TMP0) {
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gen_op_st_v(ot + s->mem_index, t0, a0);
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gen_op_st_T0_A0(ot + s->mem_index);
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} else {
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gen_op_mov_reg_v(ot, op1, t0);
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gen_op_mov_reg_T0(ot, op1);
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}
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/* update eflags. It is needed anyway most of the time, do it always. */
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/* We'll need the flags computed into CC_SRC. */
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gen_compute_eflags(s);
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assert(s->cc_op == CC_OP_EFLAGS);
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label2 = gen_new_label();
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tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
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tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
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tcg_gen_xor_tl(cpu_tmp0, t2, t0);
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tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
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tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
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tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
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/* The value that was "rotated out" is now present at the other end
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of the word. Compute C into CC_DST and O into CC_SRC2. Note that
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since we've computed the flags into CC_SRC, these variables are
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currently dead. */
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if (is_right) {
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tcg_gen_shri_tl(t0, t0, data_bits - 1);
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tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1);
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tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask);
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} else {
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tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask);
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tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1);
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}
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tcg_gen_andi_tl(t0, t0, CC_C);
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tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
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tcg_gen_andi_tl(cpu_cc_src2, cpu_cc_src2, 1);
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tcg_gen_xor_tl(cpu_cc_src2, cpu_cc_src2, cpu_cc_dst);
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gen_set_label(label2);
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/* Now conditionally store the new CC_OP value. If the shift count
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is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live.
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Otherwise reuse CC_OP_ADCOX which have the C and O flags split out
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exactly as we computed above. */
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t0 = tcg_const_i32(0);
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t1 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t1, cpu_T[1]);
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tcg_gen_movi_i32(cpu_tmp2_i32, CC_OP_ADCOX);
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tcg_gen_movi_i32(cpu_tmp3_i32, CC_OP_EFLAGS);
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tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, t1, t0,
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cpu_tmp2_i32, cpu_tmp3_i32);
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tcg_temp_free_i32(t0);
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tcg_temp_free_i32(t1);
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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tcg_temp_free(t2);
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tcg_temp_free(a0);
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/* The CC_OP value is no longer predictable. */
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set_cc_op(s, CC_OP_DYNAMIC);
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}
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static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
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int is_right)
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{
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int mask;
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int data_bits;
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TCGv t0, t1, a0;
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/* XXX: inefficient, but we must use local temps */
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t0 = tcg_temp_local_new();
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t1 = tcg_temp_local_new();
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a0 = tcg_temp_local_new();
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if (ot == OT_QUAD)
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mask = 0x3f;
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else
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mask = 0x1f;
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int mask = (ot == OT_QUAD ? 0x3f : 0x1f);
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int shift;
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/* load */
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if (op1 == OR_TMP0) {
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tcg_gen_mov_tl(a0, cpu_A0);
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gen_op_ld_v(ot + s->mem_index, t0, a0);
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gen_op_ld_T0_A0(ot + s->mem_index);
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} else {
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gen_op_mov_v_reg(ot, t0, op1);
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gen_op_mov_TN_reg(ot, 0, op1);
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}
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gen_extu(ot, t0);
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tcg_gen_mov_tl(t1, t0);
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op2 &= mask;
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data_bits = 8 << ot;
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if (op2 != 0) {
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int shift = op2 & ((1 << (3 + ot)) - 1);
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if (is_right) {
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tcg_gen_shri_tl(cpu_tmp4, t0, shift);
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tcg_gen_shli_tl(t0, t0, data_bits - shift);
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switch (ot) {
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#ifdef TARGET_X86_64
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case OT_LONG:
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tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
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if (is_right) {
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tcg_gen_rotri_i32(cpu_tmp2_i32, cpu_tmp2_i32, op2);
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} else {
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tcg_gen_rotli_i32(cpu_tmp2_i32, cpu_tmp2_i32, op2);
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}
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tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
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break;
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#endif
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default:
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if (is_right) {
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tcg_gen_rotri_tl(cpu_T[0], cpu_T[0], op2);
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} else {
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tcg_gen_rotli_tl(cpu_T[0], cpu_T[0], op2);
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}
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break;
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case OT_BYTE:
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mask = 7;
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goto do_shifts;
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case OT_WORD:
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mask = 15;
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do_shifts:
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shift = op2 & mask;
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if (is_right) {
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shift = mask + 1 - shift;
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}
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gen_extu(ot, cpu_T[0]);
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tcg_gen_shli_tl(cpu_tmp0, cpu_T[0], shift);
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tcg_gen_shri_tl(cpu_T[0], cpu_T[0], mask + 1 - shift);
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tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
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break;
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}
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else {
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tcg_gen_shli_tl(cpu_tmp4, t0, shift);
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tcg_gen_shri_tl(t0, t0, data_bits - shift);
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}
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tcg_gen_or_tl(t0, t0, cpu_tmp4);
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}
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/* store */
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if (op1 == OR_TMP0) {
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gen_op_st_v(ot + s->mem_index, t0, a0);
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gen_op_st_T0_A0(ot + s->mem_index);
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} else {
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gen_op_mov_reg_v(ot, op1, t0);
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gen_op_mov_reg_T0(ot, op1);
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}
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if (op2 != 0) {
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/* update eflags */
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/* Compute the flags into CC_SRC. */
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gen_compute_eflags(s);
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assert(s->cc_op == CC_OP_EFLAGS);
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tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
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tcg_gen_xor_tl(cpu_tmp0, t1, t0);
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tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
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tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
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tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
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/* The value that was "rotated out" is now present at the other end
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of the word. Compute C into CC_DST and O into CC_SRC2. Note that
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since we've computed the flags into CC_SRC, these variables are
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currently dead. */
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if (is_right) {
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tcg_gen_shri_tl(t0, t0, data_bits - 1);
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tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask - 1);
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tcg_gen_shri_tl(cpu_cc_dst, cpu_T[0], mask);
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} else {
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tcg_gen_shri_tl(cpu_cc_src2, cpu_T[0], mask);
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tcg_gen_andi_tl(cpu_cc_dst, cpu_T[0], 1);
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}
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tcg_gen_andi_tl(t0, t0, CC_C);
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tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
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tcg_gen_andi_tl(cpu_cc_src2, cpu_cc_src2, 1);
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tcg_gen_xor_tl(cpu_cc_src2, cpu_cc_src2, cpu_cc_dst);
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set_cc_op(s, CC_OP_ADCOX);
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}
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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tcg_temp_free(a0);
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}
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/* XXX: add faster immediate = 1 case */
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