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target/arm: Convert SHSUB, UHSUB to gvec

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240528203044.612851-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-05-28 13:30:33 -07:00 committed by Peter Maydell
parent 6ef548ed4b
commit 34c0d865a3
6 changed files with 157 additions and 45 deletions
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6
target/arm/helper.h
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@ -274,12 +274,6 @@ DEF_HELPER_2(neon_rhadd_s16, i32, i32, i32)
DEF_HELPER_2(neon_rhadd_u16, i32, i32, i32)
DEF_HELPER_2(neon_rhadd_s32, s32, s32, s32)
DEF_HELPER_2(neon_rhadd_u32, i32, i32, i32)
DEF_HELPER_2(neon_hsub_s8, i32, i32, i32)
DEF_HELPER_2(neon_hsub_u8, i32, i32, i32)
DEF_HELPER_2(neon_hsub_s16, i32, i32, i32)
DEF_HELPER_2(neon_hsub_u16, i32, i32, i32)
DEF_HELPER_2(neon_hsub_s32, s32, s32, s32)
DEF_HELPER_2(neon_hsub_u32, i32, i32, i32)
DEF_HELPER_2(neon_pmin_u8, i32, i32, i32)
DEF_HELPER_2(neon_pmin_s8, i32, i32, i32)

144
target/arm/tcg/gengvec.c
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@ -2005,3 +2005,147 @@ void gen_gvec_uhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
tcg_debug_assert(vece <= MO_32);
tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &g[vece]);
}
static void gen_shsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_andc_i64(t, b, a);
tcg_gen_vec_sar8i_i64(a, a, 1);
tcg_gen_vec_sar8i_i64(b, b, 1);
tcg_gen_andi_i64(t, t, dup_const(MO_8, 1));
tcg_gen_vec_sub8_i64(d, a, b);
tcg_gen_vec_sub8_i64(d, d, t);
}
static void gen_shsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_andc_i64(t, b, a);
tcg_gen_vec_sar16i_i64(a, a, 1);
tcg_gen_vec_sar16i_i64(b, b, 1);
tcg_gen_andi_i64(t, t, dup_const(MO_16, 1));
tcg_gen_vec_sub16_i64(d, a, b);
tcg_gen_vec_sub16_i64(d, d, t);
}
static void gen_shsub_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
TCGv_i32 t = tcg_temp_new_i32();
tcg_gen_andc_i32(t, b, a);
tcg_gen_sari_i32(a, a, 1);
tcg_gen_sari_i32(b, b, 1);
tcg_gen_andi_i32(t, t, 1);
tcg_gen_sub_i32(d, a, b);
tcg_gen_sub_i32(d, d, t);
}
static void gen_shsub_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
{
TCGv_vec t = tcg_temp_new_vec_matching(d);
tcg_gen_andc_vec(vece, t, b, a);
tcg_gen_sari_vec(vece, a, a, 1);
tcg_gen_sari_vec(vece, b, b, 1);
tcg_gen_and_vec(vece, t, t, tcg_constant_vec_matching(d, vece, 1));
tcg_gen_sub_vec(vece, d, a, b);
tcg_gen_sub_vec(vece, d, d, t);
}
void gen_gvec_shsub(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_sari_vec, INDEX_op_sub_vec, 0
};
static const GVecGen3 g[4] = {
{ .fni8 = gen_shsub8_i64,
.fniv = gen_shsub_vec,
.opt_opc = vecop_list,
.vece = MO_8 },
{ .fni8 = gen_shsub16_i64,
.fniv = gen_shsub_vec,
.opt_opc = vecop_list,
.vece = MO_16 },
{ .fni4 = gen_shsub_i32,
.fniv = gen_shsub_vec,
.opt_opc = vecop_list,
.vece = MO_32 },
};
assert(vece <= MO_32);
tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &g[vece]);
}
static void gen_uhsub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_andc_i64(t, b, a);
tcg_gen_vec_shr8i_i64(a, a, 1);
tcg_gen_vec_shr8i_i64(b, b, 1);
tcg_gen_andi_i64(t, t, dup_const(MO_8, 1));
tcg_gen_vec_sub8_i64(d, a, b);
tcg_gen_vec_sub8_i64(d, d, t);
}
static void gen_uhsub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_andc_i64(t, b, a);
tcg_gen_vec_shr16i_i64(a, a, 1);
tcg_gen_vec_shr16i_i64(b, b, 1);
tcg_gen_andi_i64(t, t, dup_const(MO_16, 1));
tcg_gen_vec_sub16_i64(d, a, b);
tcg_gen_vec_sub16_i64(d, d, t);
}
static void gen_uhsub_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
TCGv_i32 t = tcg_temp_new_i32();
tcg_gen_andc_i32(t, b, a);
tcg_gen_shri_i32(a, a, 1);
tcg_gen_shri_i32(b, b, 1);
tcg_gen_andi_i32(t, t, 1);
tcg_gen_sub_i32(d, a, b);
tcg_gen_sub_i32(d, d, t);
}
static void gen_uhsub_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
{
TCGv_vec t = tcg_temp_new_vec_matching(d);
tcg_gen_andc_vec(vece, t, b, a);
tcg_gen_shri_vec(vece, a, a, 1);
tcg_gen_shri_vec(vece, b, b, 1);
tcg_gen_and_vec(vece, t, t, tcg_constant_vec_matching(d, vece, 1));
tcg_gen_sub_vec(vece, d, a, b);
tcg_gen_sub_vec(vece, d, d, t);
}
void gen_gvec_uhsub(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_shri_vec, INDEX_op_sub_vec, 0
};
static const GVecGen3 g[4] = {
{ .fni8 = gen_uhsub8_i64,
.fniv = gen_uhsub_vec,
.opt_opc = vecop_list,
.vece = MO_8 },
{ .fni8 = gen_uhsub16_i64,
.fniv = gen_uhsub_vec,
.opt_opc = vecop_list,
.vece = MO_16 },
{ .fni4 = gen_uhsub_i32,
.fniv = gen_uhsub_vec,
.opt_opc = vecop_list,
.vece = MO_32 },
};
assert(vece <= MO_32);
tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &g[vece]);
}

27
target/arm/tcg/neon_helper.c
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@ -206,33 +206,6 @@ uint32_t HELPER(neon_rhadd_u32)(uint32_t src1, uint32_t src2)
return dest;
}
#define NEON_FN(dest, src1, src2) dest = (src1 - src2) >> 1
NEON_VOP(hsub_s8, neon_s8, 4)
NEON_VOP(hsub_u8, neon_u8, 4)
NEON_VOP(hsub_s16, neon_s16, 2)
NEON_VOP(hsub_u16, neon_u16, 2)
#undef NEON_FN
int32_t HELPER(neon_hsub_s32)(int32_t src1, int32_t src2)
{
int32_t dest;
dest = (src1 >> 1) - (src2 >> 1);
if ((~src1) & src2 & 1)
dest--;
return dest;
}
uint32_t HELPER(neon_hsub_u32)(uint32_t src1, uint32_t src2)
{
uint32_t dest;
dest = (src1 >> 1) - (src2 >> 1);
if ((~src1) & src2 & 1)
dest--;
return dest;
}
#define NEON_FN(dest, src1, src2) dest = (src1 < src2) ? src1 : src2
NEON_POP(pmin_s8, neon_s8, 4)
NEON_POP(pmin_u8, neon_u8, 4)

17
target/arm/tcg/translate-a64.c
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@ -10967,6 +10967,13 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
}
switch (opcode) {
case 0x04: /* SHSUB, UHSUB */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uhsub, size);
} else {
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_shsub, size);
}
return;
case 0x0c: /* SMAX, UMAX */
if (u) {
gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size);
@ -11044,16 +11051,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
genfn = fns[size][u];
break;
}
case 0x4: /* SHSUB, UHSUB */
{
static NeonGenTwoOpFn * const fns[3][2] = {
{ gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 },
{ gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 },
{ gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 },
};
genfn = fns[size][u];
break;
}
default:
g_assert_not_reached();
}

4
target/arm/tcg/translate-neon.c
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@ -843,6 +843,8 @@ DO_3SAME_NO_SZ_3(VPMAX_U, gen_gvec_umaxp)
DO_3SAME_NO_SZ_3(VPMIN_U, gen_gvec_uminp)
DO_3SAME_NO_SZ_3(VHADD_S, gen_gvec_shadd)
DO_3SAME_NO_SZ_3(VHADD_U, gen_gvec_uhadd)
DO_3SAME_NO_SZ_3(VHSUB_S, gen_gvec_shsub)
DO_3SAME_NO_SZ_3(VHSUB_U, gen_gvec_uhsub)
#define DO_3SAME_CMP(INSN, COND) \
static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
@ -953,8 +955,6 @@ DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1)
FUNC(d, tcg_env, n, m); \
}
DO_3SAME_32(VHSUB_S, hsub_s)
DO_3SAME_32(VHSUB_U, hsub_u)
DO_3SAME_32(VRHADD_S, rhadd_s)
DO_3SAME_32(VRHADD_U, rhadd_u)

4
target/arm/tcg/translate.h
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@ -476,6 +476,10 @@ void gen_gvec_shadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
void gen_gvec_uhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
void gen_gvec_shsub(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
void gen_gvec_uhsub(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);