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arm: switch real-time clocks to rtc_clock 

This lets the user specify the desired semantics.  By default, the RTC
will follow adjustments from the host's NTP client.  "-rtc clock=vm" will
improve determinism with both icount and qtest.  Finally, the previous
behavior is available with "-rtc clock=rt".

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Paolo Bonzini 2012-03-30 10:31:22 +00:00 committed by Peter Maydell
parent e230d4e8bd
commit 348abc86c8
4 changed files with 25 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
hw/omap1.c
View File

@ -2888,7 +2888,7 @@ static void omap_rtc_reset(struct omap_rtc_s *s)
s->pm_am = 0;
s->auto_comp = 0;
s->round = 0;
s->tick = qemu_get_clock_ms(rt_clock);
s->tick = qemu_get_clock_ms(rtc_clock);
memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
s->alarm_tm.tm_mday = 0x01;
s->status = 1 << 7;
@ -2909,7 +2909,7 @@ static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
s->irq = timerirq;
s->alarm = alarmirq;
s->clk = qemu_new_timer_ms(rt_clock, omap_rtc_tick, s);
s->clk = qemu_new_timer_ms(rtc_clock, omap_rtc_tick, s);
omap_rtc_reset(s);

26
hw/pxa2xx.c
View File

@ -875,7 +875,7 @@ static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
{
int64_t rt = qemu_get_clock_ms(rt_clock);
int64_t rt = qemu_get_clock_ms(rtc_clock);
s->last_rcnr += ((rt - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1));
s->last_rdcr += ((rt - s->last_hz) << 15) /
@ -885,7 +885,7 @@ static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
{
int64_t rt = qemu_get_clock_ms(rt_clock);
int64_t rt = qemu_get_clock_ms(rtc_clock);
if (s->rtsr & (1 << 12))
s->last_swcr += (rt - s->last_sw) / 10;
s->last_sw = rt;
@ -893,7 +893,7 @@ static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
{
int64_t rt = qemu_get_clock_ms(rt_clock);
int64_t rt = qemu_get_clock_ms(rtc_clock);
if (s->rtsr & (1 << 15))
s->last_swcr += rt - s->last_pi;
s->last_pi = rt;
@ -1019,16 +1019,16 @@ static uint64_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr,
case PIAR:
return s->piar;
case RCNR:
return s->last_rcnr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
return s->last_rcnr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1));
case RDCR:
return s->last_rdcr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
return s->last_rdcr + ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1));
case RYCR:
return s->last_rycr;
case SWCR:
if (s->rtsr & (1 << 12))
return s->last_swcr + (qemu_get_clock_ms(rt_clock) - s->last_sw) / 10;
return s->last_swcr + (qemu_get_clock_ms(rtc_clock) - s->last_sw) / 10;
else
return s->last_swcr;
default:
@ -1168,14 +1168,14 @@ static int pxa2xx_rtc_init(SysBusDevice *dev)
s->last_swcr = (tm.tm_hour << 19) |
(tm.tm_min << 13) | (tm.tm_sec << 7);
s->last_rtcpicr = 0;
s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rt_clock);
s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rtc_clock);
s->rtc_hz = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_hz_tick, s);
s->rtc_rdal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal1_tick, s);
s->rtc_rdal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal2_tick, s);
s->rtc_swal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal1_tick, s);
s->rtc_swal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal2_tick, s);
s->rtc_pi = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_pi_tick, s);
s->rtc_hz = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_hz_tick, s);
s->rtc_rdal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal1_tick, s);
s->rtc_rdal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_rdal2_tick, s);
s->rtc_swal1 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal1_tick, s);
s->rtc_swal2 = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_swal2_tick, s);
s->rtc_pi = qemu_new_timer_ms(rtc_clock, pxa2xx_rtc_pi_tick, s);
sysbus_init_irq(dev, &s->rtc_irq);

10
hw/strongarm.c
View File

@ -255,7 +255,7 @@ static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
{
int64_t rt = qemu_get_clock_ms(rt_clock);
int64_t rt = qemu_get_clock_ms(rtc_clock);
s->last_rcnr += ((rt - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1));
s->last_hz = rt;
@ -308,7 +308,7 @@ static uint64_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr,
return s->rtar;
case RCNR:
return s->last_rcnr +
((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /
(1000 * ((s->rttr & 0xffff) + 1));
default:
printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
@ -374,10 +374,10 @@ static int strongarm_rtc_init(SysBusDevice *dev)
qemu_get_timedate(&tm, 0);
s->last_rcnr = (uint32_t) mktimegm(&tm);
s->last_hz = qemu_get_clock_ms(rt_clock);
s->last_hz = qemu_get_clock_ms(rtc_clock);
s->rtc_alarm = qemu_new_timer_ms(rt_clock, strongarm_rtc_alarm_tick, s);
s->rtc_hz = qemu_new_timer_ms(rt_clock, strongarm_rtc_hz_tick, s);
s->rtc_alarm = qemu_new_timer_ms(rtc_clock, strongarm_rtc_alarm_tick, s);
s->rtc_hz = qemu_new_timer_ms(rtc_clock, strongarm_rtc_hz_tick, s);
sysbus_init_irq(dev, &s->rtc_irq);
sysbus_init_irq(dev, &s->rtc_hz_irq);

9
hw/twl92230.c
View File

@ -22,6 +22,7 @@
#include "hw.h"
#include "qemu-timer.h"
#include "i2c.h"
#include "sysemu.h"
#include "console.h"
#define VERBOSE 1
@ -71,14 +72,14 @@ static inline void menelaus_update(MenelausState *s)
static inline void menelaus_rtc_start(MenelausState *s)
{
s->rtc.next += qemu_get_clock_ms(rt_clock);
s->rtc.next += qemu_get_clock_ms(rtc_clock);
qemu_mod_timer(s->rtc.hz_tm, s->rtc.next);
}
static inline void menelaus_rtc_stop(MenelausState *s)
{
qemu_del_timer(s->rtc.hz_tm);
s->rtc.next -= qemu_get_clock_ms(rt_clock);
s->rtc.next -= qemu_get_clock_ms(rtc_clock);
if (s->rtc.next < 1)
s->rtc.next = 1;
}
@ -781,7 +782,7 @@ static void menelaus_pre_save(void *opaque)
{
MenelausState *s = opaque;
/* Should be <= 1000 */
s->rtc_next_vmstate = s->rtc.next - qemu_get_clock_ms(rt_clock);
s->rtc_next_vmstate = s->rtc.next - qemu_get_clock_ms(rtc_clock);
}
static int menelaus_post_load(void *opaque, int version_id)
@ -842,7 +843,7 @@ static int twl92230_init(I2CSlave *i2c)
{
MenelausState *s = FROM_I2C_SLAVE(MenelausState, i2c);
s->rtc.hz_tm = qemu_new_timer_ms(rt_clock, menelaus_rtc_hz, s);
s->rtc.hz_tm = qemu_new_timer_ms(rtc_clock, menelaus_rtc_hz, s);
/* Three output pins plus one interrupt pin. */
qdev_init_gpio_out(&i2c->qdev, s->out, 4);