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target/riscv: additional macros to check instruction support

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Given that the 128-bit version of the riscv spec adds new instructions, and
that some instructions that were previously only available in 64-bit mode
are now available for both 64-bit and 128-bit, we added new macros to check
for the processor mode during translation.
Although RV128 is a superset of RV64, we keep for now the RV64 only tests
for extensions other than RVI and RVM.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-5-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frédéric Pétrot 2022-01-06 22:00:54 +01:00 committed by Alistair Francis
parent e9d07601f6
commit 344b4a82fc
1 changed files with 16 additions and 4 deletions
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20
target/riscv/translate.c
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@ -443,10 +443,22 @@ EX_SH(12)
} \
} while (0)
#define REQUIRE_64BIT(ctx) do { \
if (get_xl(ctx) < MXL_RV64) { \
return false; \
} \
#define REQUIRE_64BIT(ctx) do { \
if (get_xl(ctx) != MXL_RV64) { \
return false; \
} \
} while (0)
#define REQUIRE_128BIT(ctx) do { \
if (get_xl(ctx) != MXL_RV128) { \
return false; \
} \
} while (0)
#define REQUIRE_64_OR_128BIT(ctx) do { \
if (get_xl(ctx) == MXL_RV32) { \
return false; \
} \
} while (0)
static int ex_rvc_register(DisasContext *ctx, int reg)