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ppc440: Remove ppc460ex_pcie_init legacy init function

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After previous changes we can now remove the legacy init function and
move the device creation to board code.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <29aafeea9f1c871c739600a7b093c5456e8a1dc8.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
BALATON Zoltan 2023-07-05 22:12:54 +02:00 committed by Daniel Henrique Barboza
parent 6ef62c5945
commit 340dc03c79
4 changed files with 17 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
hw/ppc/ppc440.h
View File

@ -18,6 +18,5 @@ void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
void ppc460ex_pcie_init(PowerPCCPU *cpu);
#endif /* PPC440_H */

21
hw/ppc/ppc440_uc.c
View File

@ -770,7 +770,6 @@ void ppc4xx_dma_init(CPUPPCState *env, int dcr_base)
*/
#include "hw/pci/pcie_host.h"
#define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host"
OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState, PPC460EX_PCIE_HOST)
struct PPC460EXPCIEState {
@ -799,9 +798,6 @@ struct PPC460EXPCIEState {
uint32_t cfg;
};
#define DCRN_PCIE0_BASE 0x100
#define DCRN_PCIE1_BASE 0x120
enum {
PEGPL_CFGBAH = 0x0,
PEGPL_CFGBAL,
@ -1096,20 +1092,3 @@ static void ppc460ex_pcie_register(void)
}
type_init(ppc460ex_pcie_register)
void ppc460ex_pcie_init(PowerPCCPU *cpu)
{
DeviceState *dev;
dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
qdev_prop_set_int32(dev, "busnum", 0);
qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE);
object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
qdev_prop_set_int32(dev, "busnum", 1);
qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE);
object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
}

17
hw/ppc/sam460ex.c
View File

@ -45,6 +45,9 @@
/* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \
if=updater/updater-460 of=u-boot-sam460-20100605.bin */
#define PCIE0_DCRN_BASE 0x100
#define PCIE1_DCRN_BASE 0x120
/* from Sam460 U-Boot include/configs/Sam460ex.h */
#define FLASH_BASE 0xfff00000
#define FLASH_BASE_H 0x4
@ -421,8 +424,20 @@ static void sam460ex_init(MachineState *machine)
usb_create_simple(usb_bus_find(-1), "usb-kbd");
usb_create_simple(usb_bus_find(-1), "usb-mouse");
/* PCIe buses */
dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
qdev_prop_set_int32(dev, "busnum", 0);
qdev_prop_set_int32(dev, "dcrn-base", PCIE0_DCRN_BASE);
object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
qdev_prop_set_int32(dev, "busnum", 1);
qdev_prop_set_int32(dev, "dcrn-base", PCIE1_DCRN_BASE);
object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
/* PCI bus */
ppc460ex_pcie_init(cpu);
/* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */
dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000,
qdev_get_gpio_in(uic[1], 0));

1
include/hw/ppc/ppc4xx.h
View File

@ -30,6 +30,7 @@
#include "hw/sysbus.h"
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
#define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host"
/*
* Generic DCR device