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target/riscv: Introduce mmuidx_priv

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Use the priv level encoded into the mmu_idx, rather than
starting from env->priv.  We have already checked MPRV+MPP
in riscv_cpu_mmu_index -- no need to repeat that.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230325105429.1142530-14-richard.henderson@linaro.org>
Message-Id: <20230412114333.118895-14-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2023-04-12 13:43:21 +02:00 committed by Alistair Francis
parent 4005a799f1
commit 340b5805db
2 changed files with 10 additions and 5 deletions
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6
target/riscv/cpu_helper.c
View File

@ -758,7 +758,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
*/
MemTxResult res;
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int mode = env->priv;
int mode = mmuidx_priv(mmu_idx);
bool use_background = false;
hwaddr ppn;
int napot_bits = 0;
@ -781,10 +781,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
*/
if (riscv_cpu_two_stage_lookup(mmu_idx)) {
mode = get_field(env->hstatus, HSTATUS_SPVP);
} else if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
}
}
if (first_stage == false) {

9
target/riscv/internals.h
View File

@ -37,6 +37,15 @@
#define MMUIdx_M 3
#define MMU_2STAGE_BIT (1 << 2)
static inline int mmuidx_priv(int mmu_idx)
{
int ret = mmu_idx & 3;
if (ret == MMUIdx_S_SUM) {
ret = PRV_S;
}
return ret;
}
static inline bool mmuidx_sum(int mmu_idx)
{
return (mmu_idx & 3) == MMUIdx_S_SUM;