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hw/arm/armsse: Add a define for number of IRQs used by the SSE itself

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The SSE uses 32 interrupts for its own devices, and then passes through
its expansion IRQ inputs to the CPU's interrupts 33 and upward.
Add a define for the number of IRQs the SSE uses for itself, instead
of hardcoding 32.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-23-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-02-19 14:45:55 +00:00
parent 91eb4f64eb
commit 3378873802
2 changed files with 6 additions and 3 deletions
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4
hw/arm/armsse.c
View File

@ -531,7 +531,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
int j;
char *gpioname;
qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32);
qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IRQS);
/*
* In real hardware the initial Secure VTOR is set from the INITSVTOR*
* registers in the IoT Kit System Control Register block. In QEMU
@ -602,7 +602,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
/* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */
s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq);
for (j = 0; j < s->exp_numirq; j++) {
s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32);
s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + NUM_SSE_IRQS);
}
if (i == 0) {
gpioname = g_strdup("EXP_IRQ");

5
include/hw/arm/armsse.h
View File

@ -145,6 +145,9 @@ OBJECT_DECLARE_TYPE(ARMSSE, ARMSSEClass,
#define RAM3_PPU 6
#define NUM_PPUS 7
/* Number of CPU IRQs used by the SSE itself */
#define NUM_SSE_IRQS 32
struct ARMSSE {
/*< private >*/
SysBusDevice parent_obj;
@ -165,7 +168,7 @@ struct ARMSSE {
qemu_or_irq mpc_irq_orgate;
qemu_or_irq nmi_orgate;
SplitIRQ cpu_irq_splitter[32];
SplitIRQ cpu_irq_splitter[NUM_SSE_IRQS];
CMSDKAPBDualTimer dualtimer;