target/sparc: Add feature bits for VIS 3
The manual separates VIS 3 and VIS 3B, even though they are both present in all extant cpus. For clarity, let the translator match the manual but otherwise leave them on the same feature bit. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
4fd71d19ac
commit
3335a04806
@ -13,3 +13,4 @@ FEATURE(CACHE_CTRL)
|
|||||||
FEATURE(POWERDOWN)
|
FEATURE(POWERDOWN)
|
||||||
FEATURE(CASA)
|
FEATURE(CASA)
|
||||||
FEATURE(FMAF)
|
FEATURE(FMAF)
|
||||||
|
FEATURE(VIS3)
|
||||||
|
@ -2188,6 +2188,8 @@ static int extract_qfpreg(DisasContext *dc, int x)
|
|||||||
# define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV)
|
# define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV)
|
||||||
# define avail_VIS1(C) ((C)->def->features & CPU_FEATURE_VIS1)
|
# define avail_VIS1(C) ((C)->def->features & CPU_FEATURE_VIS1)
|
||||||
# define avail_VIS2(C) ((C)->def->features & CPU_FEATURE_VIS2)
|
# define avail_VIS2(C) ((C)->def->features & CPU_FEATURE_VIS2)
|
||||||
|
# define avail_VIS3(C) ((C)->def->features & CPU_FEATURE_VIS3)
|
||||||
|
# define avail_VIS3B(C) avail_VIS3(C)
|
||||||
#else
|
#else
|
||||||
# define avail_32(C) true
|
# define avail_32(C) true
|
||||||
# define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17)
|
# define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17)
|
||||||
@ -2201,6 +2203,8 @@ static int extract_qfpreg(DisasContext *dc, int x)
|
|||||||
# define avail_HYPV(C) false
|
# define avail_HYPV(C) false
|
||||||
# define avail_VIS1(C) false
|
# define avail_VIS1(C) false
|
||||||
# define avail_VIS2(C) false
|
# define avail_VIS2(C) false
|
||||||
|
# define avail_VIS3(C) false
|
||||||
|
# define avail_VIS3B(C) false
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Default case for non jump instructions. */
|
/* Default case for non jump instructions. */
|
||||||
|
Loading…
Reference in New Issue
Block a user