tcg-mips: Adjust load/store functions for mips64
tcg_out_ldst: using a generic ALIAS_PADD to avoid ifdefs tcg_out_ld: generates LD or LW tcg_out_st: generates SD or SW Tested-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: James Hogan <james.hogan@imgtec.com> Tested-by: YunQiang Su <wzssyqa@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Jin Guojie <jinguojie@loongson.cn> Message-Id: <1483592275-4496-7-git-send-email-jinguojie@loongson.cn>
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@ -697,7 +697,7 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
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if (ofs != lo) {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
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if (addr != TCG_REG_ZERO) {
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tcg_out_opc_reg(s, OPC_ADDU, TCG_TMP0, TCG_TMP0, addr);
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tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
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}
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addr = TCG_TMP0;
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}
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@ -707,13 +707,21 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
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static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
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TCGReg arg1, intptr_t arg2)
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{
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tcg_out_ldst(s, OPC_LW, arg, arg1, arg2);
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MIPSInsn opc = OPC_LD;
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if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
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opc = OPC_LW;
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}
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tcg_out_ldst(s, opc, arg, arg1, arg2);
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}
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static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
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TCGReg arg1, intptr_t arg2)
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{
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tcg_out_ldst(s, OPC_SW, arg, arg1, arg2);
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MIPSInsn opc = OPC_SD;
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if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
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opc = OPC_SW;
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}
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tcg_out_ldst(s, opc, arg, arg1, arg2);
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}
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static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
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