target-ppc: introduce opc4 for Expanded Opcode
ISA 3.0 has introduced EO - Expanded Opcode. Introduce third level indirect opcode table and corresponding parsing routines. EO (11:12) Expanded opcode field Formats: XX1 EO (11:15) Expanded opcode field Formats: VX, X, XX2 Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> [dwg: Trivial checkpatch fixup] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Nikunj A Dadhania
David Gibson
parent
5f29cc8292
commit
323ad19bcc
@ -367,12 +367,13 @@ GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
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#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
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GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
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#define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
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GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
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typedef struct opcode_t {
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unsigned char opc1, opc2, opc3;
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unsigned char opc1, opc2, opc3, opc4;
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#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
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unsigned char pad[5];
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#else
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unsigned char pad[1];
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unsigned char pad[4];
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#endif
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opc_handler_t handler;
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const char *oname;
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@ -452,6 +453,8 @@ EXTRACT_HELPER(opc1, 26, 6);
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EXTRACT_HELPER(opc2, 1, 5);
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/* Opcode part 3 */
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EXTRACT_HELPER(opc3, 6, 5);
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/* Opcode part 4 */
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EXTRACT_HELPER(opc4, 16, 5);
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/* Update Cr0 flags */
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EXTRACT_HELPER(Rc, 0, 1);
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/* Update Cr6 flags (Altivec) */
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@ -589,7 +592,7 @@ EXTRACT_HELPER(SP, 19, 2);
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.opc1 = op1, \
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.opc2 = op2, \
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.opc3 = op3, \
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.pad = { 0, }, \
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.opc4 = 0xff, \
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.handler = { \
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.inval1 = invl, \
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.type = _typ, \
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@ -604,7 +607,7 @@ EXTRACT_HELPER(SP, 19, 2);
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.opc1 = op1, \
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.opc2 = op2, \
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.opc3 = op3, \
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.pad = { 0, }, \
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.opc4 = 0xff, \
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.handler = { \
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.inval1 = invl1, \
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.inval2 = invl2, \
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@ -620,7 +623,7 @@ EXTRACT_HELPER(SP, 19, 2);
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.opc1 = op1, \
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.opc2 = op2, \
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.opc3 = op3, \
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.pad = { 0, }, \
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.opc4 = 0xff, \
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.handler = { \
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.inval1 = invl, \
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.type = _typ, \
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@ -630,13 +633,28 @@ EXTRACT_HELPER(SP, 19, 2);
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}, \
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.oname = onam, \
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}
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#define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
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{ \
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.opc1 = op1, \
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.opc2 = op2, \
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.opc3 = op3, \
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.opc4 = op4, \
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.handler = { \
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.inval1 = invl, \
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.type = _typ, \
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.type2 = _typ2, \
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.handler = &gen_##name, \
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.oname = stringify(name), \
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}, \
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.oname = stringify(name), \
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}
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#else
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#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
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{ \
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.opc1 = op1, \
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.opc2 = op2, \
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.opc3 = op3, \
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.pad = { 0, }, \
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.opc4 = 0xff, \
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.handler = { \
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.inval1 = invl, \
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.type = _typ, \
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@ -650,7 +668,7 @@ EXTRACT_HELPER(SP, 19, 2);
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.opc1 = op1, \
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.opc2 = op2, \
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.opc3 = op3, \
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.pad = { 0, }, \
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.opc4 = 0xff, \
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.handler = { \
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.inval1 = invl1, \
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.inval2 = invl2, \
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@ -665,7 +683,7 @@ EXTRACT_HELPER(SP, 19, 2);
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.opc1 = op1, \
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.opc2 = op2, \
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.opc3 = op3, \
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.pad = { 0, }, \
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.opc4 = 0xff, \
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.handler = { \
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.inval1 = invl, \
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.type = _typ, \
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@ -674,6 +692,20 @@ EXTRACT_HELPER(SP, 19, 2);
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}, \
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.oname = onam, \
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}
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#define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
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{ \
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.opc1 = op1, \
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.opc2 = op2, \
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.opc3 = op3, \
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.opc4 = op4, \
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.handler = { \
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.inval1 = invl, \
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.type = _typ, \
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.type2 = _typ2, \
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.handler = &gen_##name, \
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}, \
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.oname = stringify(name), \
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}
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#endif
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/* SPR load/store helpers */
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@ -11905,9 +11937,10 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
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} else {
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ctx.opcode = cpu_ldl_code(env, ctx.nip);
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}
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LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
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ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
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opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
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LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
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ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
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opc3(ctx.opcode), opc4(ctx.opcode),
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ctx.le_mode ? "little" : "big");
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ctx.nip += 4;
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table = env->opcodes;
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handler = table[opc1(ctx.opcode)];
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@ -11917,14 +11950,20 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
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if (is_indirect_opcode(handler)) {
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table = ind_table(handler);
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handler = table[opc3(ctx.opcode)];
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if (is_indirect_opcode(handler)) {
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table = ind_table(handler);
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handler = table[opc4(ctx.opcode)];
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}
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}
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}
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/* Is opcode *REALLY* valid ? */
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if (unlikely(handler->handler == &gen_invalid)) {
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qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
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"%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
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"%02x - %02x - %02x - %02x (%08x) "
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TARGET_FMT_lx " %d\n",
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opc1(ctx.opcode), opc2(ctx.opcode),
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opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
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opc3(ctx.opcode), opc4(ctx.opcode),
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ctx.opcode, ctx.nip - 4, (int)msr_ir);
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} else {
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uint32_t inval;
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@ -11936,9 +11975,10 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
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if (unlikely((ctx.opcode & inval) != 0)) {
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qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
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"%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
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ctx.opcode & inval, opc1(ctx.opcode),
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opc2(ctx.opcode), opc3(ctx.opcode),
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"%02x - %02x - %02x - %02x (%08x) "
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TARGET_FMT_lx "\n", ctx.opcode & inval,
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opc1(ctx.opcode), opc2(ctx.opcode),
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opc3(ctx.opcode), opc4(ctx.opcode),
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ctx.opcode, ctx.nip - 4);
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gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
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break;
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@ -11965,9 +12005,9 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
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break;
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}
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if (tcg_check_temp_count()) {
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fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
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opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
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ctx.opcode);
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fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
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"temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
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opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
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exit(1);
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}
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}
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@ -9253,13 +9253,47 @@ static int register_dblind_insn (opc_handler_t **ppc_opcodes,
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return 0;
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}
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static int register_trplind_insn(opc_handler_t **ppc_opcodes,
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unsigned char idx1, unsigned char idx2,
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unsigned char idx3, unsigned char idx4,
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opc_handler_t *handler)
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{
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opc_handler_t **table;
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if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
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printf("*** ERROR: unable to join indirect table idx "
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"[%02x-%02x]\n", idx1, idx2);
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return -1;
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}
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table = ind_table(ppc_opcodes[idx1]);
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if (register_ind_in_table(table, idx2, idx3, NULL) < 0) {
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printf("*** ERROR: unable to join 2nd-level indirect table idx "
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"[%02x-%02x-%02x]\n", idx1, idx2, idx3);
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return -1;
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}
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table = ind_table(table[idx2]);
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if (register_ind_in_table(table, idx3, idx4, handler) < 0) {
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printf("*** ERROR: unable to insert opcode "
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"[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4);
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return -1;
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}
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return 0;
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}
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static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
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{
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if (insn->opc2 != 0xFF) {
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if (insn->opc3 != 0xFF) {
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if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
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insn->opc3, &insn->handler) < 0)
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return -1;
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if (insn->opc4 != 0xFF) {
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if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2,
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insn->opc3, insn->opc4,
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&insn->handler) < 0) {
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return -1;
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}
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} else {
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if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
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insn->opc3, &insn->handler) < 0)
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return -1;
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}
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} else {
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if (register_ind_insn(ppc_opcodes, insn->opc1,
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insn->opc2, &insn->handler) < 0)
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@ -9335,7 +9369,7 @@ static void dump_ppc_insns (CPUPPCState *env)
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{
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opc_handler_t **table, *handler;
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const char *p, *q;
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uint8_t opc1, opc2, opc3;
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uint8_t opc1, opc2, opc3, opc4;
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printf("Instructions set:\n");
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/* opc1 is 6 bits long */
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@ -9355,34 +9389,51 @@ static void dump_ppc_insns (CPUPPCState *env)
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for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
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opc3++) {
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handler = table[opc3];
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if (handler->handler != &gen_invalid) {
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/* Special hack to properly dump SPE insns */
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p = strchr(handler->oname, '_');
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if (p == NULL) {
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printf("INSN: %02x %02x %02x (%02d %04d) : "
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"%s\n",
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opc1, opc2, opc3, opc1,
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(opc3 << 5) | opc2,
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handler->oname);
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} else {
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q = "speundef";
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if ((p - handler->oname) != strlen(q) ||
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memcmp(handler->oname, q, strlen(q)) != 0) {
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/* First instruction */
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printf("INSN: %02x %02x %02x (%02d %04d) : "
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"%.*s\n",
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opc1, opc2 << 1, opc3, opc1,
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(opc3 << 6) | (opc2 << 1),
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(int)(p - handler->oname),
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if (is_indirect_opcode(handler)) {
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table = ind_table(handler);
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/* opc4 is 5 bits long */
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for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN;
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opc4++) {
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handler = table[opc4];
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if (handler->handler != &gen_invalid) {
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printf("INSN: %02x %02x %02x %02x -- "
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"(%02d %04d %02d) : %s\n",
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opc1, opc2, opc3, opc4,
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opc1, (opc3 << 5) | opc2, opc4,
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handler->oname);
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}
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if (strcmp(p + 1, q) != 0) {
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/* Second instruction */
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}
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} else {
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if (handler->handler != &gen_invalid) {
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/* Special hack to properly dump SPE insns */
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p = strchr(handler->oname, '_');
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if (p == NULL) {
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printf("INSN: %02x %02x %02x (%02d %04d) : "
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"%s\n",
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opc1, (opc2 << 1) | 1, opc3, opc1,
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(opc3 << 6) | (opc2 << 1) | 1,
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p + 1);
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opc1, opc2, opc3, opc1,
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(opc3 << 5) | opc2,
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handler->oname);
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} else {
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q = "speundef";
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if ((p - handler->oname) != strlen(q)
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|| (memcmp(handler->oname, q, strlen(q))
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!= 0)) {
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/* First instruction */
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printf("INSN: %02x %02x %02x"
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"(%02d %04d) : %.*s\n",
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opc1, opc2 << 1, opc3, opc1,
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(opc3 << 6) | (opc2 << 1),
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(int)(p - handler->oname),
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handler->oname);
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}
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if (strcmp(p + 1, q) != 0) {
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/* Second instruction */
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printf("INSN: %02x %02x %02x "
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"(%02d %04d) : %s\n", opc1,
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(opc2 << 1) | 1, opc3, opc1,
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(opc3 << 6) | (opc2 << 1) | 1,
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p + 1);
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}
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}
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}
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}
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@ -9858,8 +9909,8 @@ static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
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{
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PowerPCCPU *cpu = POWERPC_CPU(dev);
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CPUPPCState *env = &cpu->env;
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opc_handler_t **table;
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int i, j;
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opc_handler_t **table, **table_2;
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int i, j, k;
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cpu_exec_exit(CPU(dev));
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@ -9870,10 +9921,20 @@ static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
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if (is_indirect_opcode(env->opcodes[i])) {
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table = ind_table(env->opcodes[i]);
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for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
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if (table[j] != &invalid_handler &&
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is_indirect_opcode(table[j])) {
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if (table[j] == &invalid_handler) {
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continue;
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}
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if (is_indirect_opcode(table[j])) {
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table_2 = ind_table(table[j]);
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for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) {
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if (table_2[k] != &invalid_handler &&
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is_indirect_opcode(table_2[k])) {
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g_free((opc_handler_t *)((uintptr_t)table_2[k] &
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~PPC_INDIRECT));
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}
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}
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g_free((opc_handler_t *)((uintptr_t)table[j] &
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~PPC_INDIRECT));
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~PPC_INDIRECT));
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}
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}
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g_free((opc_handler_t *)((uintptr_t)env->opcodes[i] &
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