hw/arm/aspeed: Add the i3c device to the AST2600 SoC
Add the new i3c device to the AST2600 SoC. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Reviewed-by: Graeme Gregory <quic_ggregory@quicinc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Graeme Gregory <quic_ggregory@quicinc.com> Message-id: 20220111084546.4145785-3-troy_lee@aspeedtech.com [PMM: tidied commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -61,6 +61,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
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[ASPEED_DEV_UART1] = 0x1E783000,
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[ASPEED_DEV_UART1] = 0x1E783000,
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[ASPEED_DEV_UART5] = 0x1E784000,
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[ASPEED_DEV_UART5] = 0x1E784000,
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[ASPEED_DEV_VUART] = 0x1E787000,
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[ASPEED_DEV_VUART] = 0x1E787000,
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[ASPEED_DEV_I3C] = 0x1E7A0000,
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[ASPEED_DEV_SDRAM] = 0x80000000,
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[ASPEED_DEV_SDRAM] = 0x80000000,
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};
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};
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@ -108,6 +109,7 @@ static const int aspeed_soc_ast2600_irqmap[] = {
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[ASPEED_DEV_ETH4] = 33,
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[ASPEED_DEV_ETH4] = 33,
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[ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
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[ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
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[ASPEED_DEV_DP] = 62,
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[ASPEED_DEV_DP] = 62,
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[ASPEED_DEV_I3C] = 102, /* 102 -> 107 */
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};
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};
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static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
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static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
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@ -223,6 +225,8 @@ static void aspeed_soc_ast2600_init(Object *obj)
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snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
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snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
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object_initialize_child(obj, "hace", &s->hace, typename);
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object_initialize_child(obj, "hace", &s->hace, typename);
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object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
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}
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}
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/*
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/*
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@ -523,6 +527,18 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
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aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
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/* I3C */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
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for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
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qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
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sc->irqmap[ASPEED_DEV_I3C] + i);
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/* The AST2600 I3C controller has one IRQ per bus. */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
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}
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}
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}
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static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
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static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
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@ -21,6 +21,7 @@
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#include "hw/timer/aspeed_timer.h"
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#include "hw/timer/aspeed_timer.h"
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#include "hw/rtc/aspeed_rtc.h"
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#include "hw/rtc/aspeed_rtc.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "hw/misc/aspeed_i3c.h"
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#include "hw/ssi/aspeed_smc.h"
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#include "hw/ssi/aspeed_smc.h"
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#include "hw/misc/aspeed_hace.h"
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#include "hw/misc/aspeed_hace.h"
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#include "hw/watchdog/wdt_aspeed.h"
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#include "hw/watchdog/wdt_aspeed.h"
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@ -51,6 +52,7 @@ struct AspeedSoCState {
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AspeedRtcState rtc;
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AspeedRtcState rtc;
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AspeedTimerCtrlState timerctrl;
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AspeedTimerCtrlState timerctrl;
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AspeedI2CState i2c;
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AspeedI2CState i2c;
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AspeedI3CState i3c;
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AspeedSCUState scu;
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AspeedSCUState scu;
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AspeedHACEState hace;
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AspeedHACEState hace;
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AspeedXDMAState xdma;
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AspeedXDMAState xdma;
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@ -141,6 +143,7 @@ enum {
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ASPEED_DEV_HACE,
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ASPEED_DEV_HACE,
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ASPEED_DEV_DPMCU,
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ASPEED_DEV_DPMCU,
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ASPEED_DEV_DP,
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ASPEED_DEV_DP,
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ASPEED_DEV_I3C,
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};
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};
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#endif /* ASPEED_SOC_H */
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#endif /* ASPEED_SOC_H */
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