mirror of https://gitlab.com/qemu-project/qemu
target/riscv: debug: Introduce tinfo CSR
tinfo.info: One bit for each possible type enumerated in tdata1. If the bit is set, then that type is supported by the currently selected trigger. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20220909134215.1843865-6-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -319,6 +319,7 @@
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#define CSR_TDATA1 0x7a1
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#define CSR_TDATA1 0x7a1
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#define CSR_TDATA2 0x7a2
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#define CSR_TDATA2 0x7a2
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#define CSR_TDATA3 0x7a3
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#define CSR_TDATA3 0x7a3
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#define CSR_TINFO 0x7a4
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/* Debug Mode Registers */
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/* Debug Mode Registers */
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#define CSR_DCSR 0x7b0
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#define CSR_DCSR 0x7b0
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@ -3094,6 +3094,13 @@ static RISCVException write_tdata(CPURISCVState *env, int csrno,
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return RISCV_EXCP_NONE;
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return RISCV_EXCP_NONE;
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}
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}
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static RISCVException read_tinfo(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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*val = tinfo_csr_read(env);
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return RISCV_EXCP_NONE;
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}
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/*
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/*
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* Functions to access Pointer Masking feature registers
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* Functions to access Pointer Masking feature registers
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* We have to check if current priv lvl could modify
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* We have to check if current priv lvl could modify
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@ -3898,6 +3905,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata },
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[CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata },
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[CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata },
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[CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata },
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[CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },
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[CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },
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[CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore },
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/* User Pointer Masking */
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/* User Pointer Masking */
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[CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
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[CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
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@ -37,9 +37,7 @@
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* - tdata1
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* - tdata1
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* - tdata2
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* - tdata2
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* - tdata3
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* - tdata3
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*
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* - tinfo
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* We don't support writable 'type' field in the tdata1 register, so there is
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* no need to implement the "tinfo" CSR.
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*
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*
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* The following triggers are implemented:
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* The following triggers are implemented:
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*
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*
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@ -372,6 +370,12 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
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}
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}
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}
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}
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target_ulong tinfo_csr_read(CPURISCVState *env)
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{
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/* assume all triggers support the same types of triggers */
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return BIT(TRIGGER_TYPE_AD_MATCH);
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}
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void riscv_cpu_debug_excp_handler(CPUState *cs)
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void riscv_cpu_debug_excp_handler(CPUState *cs)
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{
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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RISCVCPU *cpu = RISCV_CPU(cs);
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@ -95,6 +95,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong val);
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target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
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target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
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void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
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void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
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target_ulong tinfo_csr_read(CPURISCVState *env);
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void riscv_cpu_debug_excp_handler(CPUState *cs);
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void riscv_cpu_debug_excp_handler(CPUState *cs);
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bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
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bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
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bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
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bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
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