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hw/dma/xilinx_axidma: Check DMASR.HALTED to prevent infinite loop.

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When we receive a packet from the xilinx_axienet and then try to s2mem
through the xilinx_axidma, if the descriptor ring buffer is full in the
xilinx axidma driver, we’ll assert the DMASR.HALTED in the
function : stream_process_s2mem and return 0. In the end, we’ll be stuck in
an infinite loop in axienet_eth_rx_notify.

This patch checks the DMASR.HALTED state when we try to push data
from xilinx axi-enet to xilinx axi-dma. When the DMASR.HALTED is asserted,
we will not keep pushing the data and then prevent the infinte loop.

Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20230519062137.1251741-1-tommy.wu@sifive.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Tommy Wu 2023-05-25 10:37:51 +01:00 committed by Peter Maydell
parent 8cefcc3b71
commit 31afe04586
1 changed files with 8 additions and 3 deletions
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11
hw/dma/xilinx_axidma.c
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@ -168,6 +168,11 @@ static inline int stream_idle(struct Stream *s)
return !!(s->regs[R_DMASR] & DMASR_IDLE); return !!(s->regs[R_DMASR] & DMASR_IDLE);
} }
static inline int stream_halted(struct Stream *s)
{
return !!(s->regs[R_DMASR] & DMASR_HALTED);
}
static void stream_reset(struct Stream *s) static void stream_reset(struct Stream *s)
{ {
s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */ s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */
@ -269,7 +274,7 @@ static void stream_process_mem2s(struct Stream *s, StreamSink *tx_data_dev,
uint64_t addr; uint64_t addr;
bool eop; bool eop;
if (!stream_running(s) || stream_idle(s)) { if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
return; return;
} }
@ -326,7 +331,7 @@ static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf,
unsigned int rxlen; unsigned int rxlen;
size_t pos = 0; size_t pos = 0;
if (!stream_running(s) || stream_idle(s)) { if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
return 0; return 0;
} }
@ -407,7 +412,7 @@ xilinx_axidma_data_stream_can_push(StreamSink *obj,
XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj); XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
struct Stream *s = &ds->dma->streams[1]; struct Stream *s = &ds->dma->streams[1];
if (!stream_running(s) || stream_idle(s)) { if (!stream_running(s) || stream_idle(s) || stream_halted(s)) {
ds->dma->notify = notify; ds->dma->notify = notify;
ds->dma->notify_opaque = notify_opaque; ds->dma->notify_opaque = notify_opaque;
return false; return false;