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escc: update the R_SPEC register SPEC_ALLSENT bit when writing to W_TXCTRL1

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The ESCC datasheet states that SPEC_ALLSENT is always set in sync mode and set
in async mode once all characters have cleared the transmitter. Since writes to
SERIAL_DATA use a synchronous chardev API, the guest can never see the state when
transmission is in progress so it is possible to set SPEC_ALLSENT in the
R_SPEC register unconditionally.

This fixes a hang when using the Sun PROM as it attempts to enumerate the
onboard serial devices, and a similar hang in OpenBSD SPARC32 where in both cases
the boot process will not proceed until SPEC_ALLSENT has been set after writing
to W_TXCTRL1.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20211118181835.18497-3-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Mark Cave-Ayland 2021-11-18 18:18:35 +00:00
parent c29cd47e82
commit 319e89cdc3
1 changed files with 14 additions and 0 deletions
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14
hw/char/escc.c
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@ -586,6 +586,20 @@ static void escc_mem_write(void *opaque, hwaddr addr,
s->wregs[s->reg] = val;
break;
case W_TXCTRL1:
s->wregs[s->reg] = val;
/*
* The ESCC datasheet states that SPEC_ALLSENT is always set in
* sync mode, and set in async mode when all characters have
* cleared the transmitter. Since writes to SERIAL_DATA use the
* blocking qemu_chr_fe_write_all() function to write each
* character, the guest can never see the state when async data
* is in the process of being transmitted so we can set this bit
* unconditionally regardless of the state of the W_TXCTRL1 mode
* bits.
*/
s->rregs[R_SPEC] |= SPEC_ALLSENT;
escc_update_parameters(s);
break;
case W_TXCTRL2:
s->wregs[s->reg] = val;
escc_update_parameters(s);