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target-arm queue:

Browse Source 
* hw/arm/mps2-tz.c: fix RX/TX interrupts order
  * accel/kvm/kvm-all: Fixes the missing break in vCPU unpark logic
  * target/arm: Handle denormals correctly for FMOPA (widening)
  * target/xtensa: Correct assert condition in handle_interrupt()
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Merge tag 'pull-target-arm-20240801' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/arm/mps2-tz.c: fix RX/TX interrupts order
 * accel/kvm/kvm-all: Fixes the missing break in vCPU unpark logic
 * target/arm: Handle denormals correctly for FMOPA (widening)
 * target/xtensa: Correct assert condition in handle_interrupt()

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# gpg: Signature made Fri 02 Aug 2024 12:22:35 AM AEST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]

* tag 'pull-target-arm-20240801' of https://git.linaro.org/people/pmaydell/qemu-arm:
  target/xtensa: Correct assert condition in handle_interrupt()
  target/arm: Handle denormals correctly for FMOPA (widening)
  accel/kvm/kvm-all: Fixes the missing break in vCPU unpark logic
  hw/arm/mps2-tz.c: fix RX/TX interrupts order

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-08-02 08:18:37 +10:00
commit 31669121a0
6 changed files with 56 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
accel/kvm/kvm-all.c
View File

@ -362,6 +362,7 @@ int kvm_unpark_vcpu(KVMState *s, unsigned long vcpu_id)
QLIST_REMOVE(cpu, node);
kvm_fd = cpu->kvm_fd;
g_free(cpu);
break;
}
}

6
hw/arm/mps2-tz.c
View File

@ -435,7 +435,7 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
const char *name, hwaddr size,
const int *irqs, const PPCExtraData *extradata)
{
/* The irq[] array is tx, rx, combined, in that order */
/* The irq[] array is rx, tx, combined, in that order */
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
CMSDKAPBUART *uart = opaque;
int i = uart - &mms->uart[0];
@ -447,8 +447,8 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq);
sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
s = SYS_BUS_DEVICE(uart);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0]));
sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1]));
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[1]));
sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[0]));
sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2]));

2
target/arm/tcg/helper-sme.h
View File

@ -121,7 +121,7 @@ DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_7(sme_fmopa_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
void, ptr, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG,

39
target/arm/tcg/sme_helper.c
View File

@ -992,12 +992,23 @@ static inline uint32_t f16mop_adj_pair(uint32_t pair, uint32_t pg, uint32_t neg)
}
static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2,
float_status *s_std, float_status *s_odd)
float_status *s_f16, float_status *s_std,
float_status *s_odd)
{
float64 e1r = float16_to_float64(e1 & 0xffff, true, s_std);
float64 e1c = float16_to_float64(e1 >> 16, true, s_std);
float64 e2r = float16_to_float64(e2 & 0xffff, true, s_std);
float64 e2c = float16_to_float64(e2 >> 16, true, s_std);
/*
* We need three different float_status for different parts of this
* operation:
* - the input conversion of the float16 values must use the
* f16-specific float_status, so that the FPCR.FZ16 control is applied
* - operations on float32 including the final accumulation must use
* the normal float_status, so that FPCR.FZ is applied
* - we have pre-set-up copy of s_std which is set to round-to-odd,
* for the multiply (see below)
*/
float64 e1r = float16_to_float64(e1 & 0xffff, true, s_f16);
float64 e1c = float16_to_float64(e1 >> 16, true, s_f16);
float64 e2r = float16_to_float64(e2 & 0xffff, true, s_f16);
float64 e2c = float16_to_float64(e2 >> 16, true, s_f16);
float64 t64;
float32 t32;
@ -1019,20 +1030,23 @@ static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2,
}
void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn,
void *vpm, void *vst, uint32_t desc)
void *vpm, CPUARMState *env, uint32_t desc)
{
intptr_t row, col, oprsz = simd_maxsz(desc);
uint32_t neg = simd_data(desc) * 0x80008000u;
uint16_t *pn = vpn, *pm = vpm;
float_status fpst_odd, fpst_std;
float_status fpst_odd, fpst_std, fpst_f16;
/*
* Make a copy of float_status because this operation does not
* update the cumulative fp exception status. It also produces
* default nans. Make a second copy with round-to-odd -- see above.
* Make copies of fp_status and fp_status_f16, because this operation
* does not update the cumulative fp exception status. It also
* produces default NaNs. We also need a second copy of fp_status with
* round-to-odd -- see above.
*/
fpst_std = *(float_status *)vst;
fpst_f16 = env->vfp.fp_status_f16;
fpst_std = env->vfp.fp_status;
set_default_nan_mode(true, &fpst_std);
set_default_nan_mode(true, &fpst_f16);
fpst_odd = fpst_std;
set_float_rounding_mode(float_round_to_odd, &fpst_odd);
@ -1052,7 +1066,8 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm, void *vpn,
uint32_t m = *(uint32_t *)(vzm + H1_4(col));
m = f16mop_adj_pair(m, pcol, 0);
*a = f16_dotadd(*a, n, m, &fpst_std, &fpst_odd);
*a = f16_dotadd(*a, n, m,
&fpst_f16, &fpst_std, &fpst_odd);
}
col += 4;
pcol >>= 4;

25
target/arm/tcg/translate-sme.c
View File

@ -334,8 +334,29 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
return true;
}
TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_fpst, a,
MO_32, FPST_FPCR_F16, gen_helper_sme_fmopa_h)
static bool do_outprod_env(DisasContext *s, arg_op *a, MemOp esz,
gen_helper_gvec_5_ptr *fn)
{
int svl = streaming_vec_reg_size(s);
uint32_t desc = simd_desc(svl, svl, a->sub);
TCGv_ptr za, zn, zm, pn, pm;
if (!sme_smza_enabled_check(s)) {
return true;
}
za = get_tile(s, esz, a->zad);
zn = vec_full_reg_ptr(s, a->zn);
zm = vec_full_reg_ptr(s, a->zm);
pn = pred_full_reg_ptr(s, a->pn);
pm = pred_full_reg_ptr(s, a->pm);
fn(za, zn, zm, pn, pm, tcg_env, tcg_constant_i32(desc));
return true;
}
TRANS_FEAT(FMOPA_h, aa64_sme, do_outprod_env, a,
MO_32, gen_helper_sme_fmopa_h)
TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, a,
MO_32, FPST_FPCR, gen_helper_sme_fmopa_s)
TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, a,

2
target/xtensa/exc_helper.c
View File

@ -171,7 +171,7 @@ static void handle_interrupt(CPUXtensaState *env)
if (level > 1) {
/* env->config->nlevel check should have ensured this */
assert(level < sizeof(env->config->interrupt_vector));
assert(level < ARRAY_SIZE(env->config->interrupt_vector));
env->sregs[EPC1 + level - 1] = env->pc;
env->sregs[EPS2 + level - 2] = env->sregs[PS];