target/riscv: Avoid tcg_const_*
All uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -209,8 +209,8 @@ static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a)
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static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a)
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{
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TCGv s1 = tcg_const_tl(a->rs1);
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TCGv s2 = tcg_const_tl(a->zimm);
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TCGv s1 = tcg_constant_tl(a->rs1);
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TCGv s2 = tcg_constant_tl(a->zimm);
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return do_vsetivli(s, a->rd, s1, s2);
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}
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@ -299,7 +299,7 @@ static bool trans_fsgnjn_h(DisasContext *ctx, arg_fsgnjn_h *a)
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* Replace bit 15 in rs1 with inverse in rs2.
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* This formulation retains the nanboxing of rs1.
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*/
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mask = tcg_const_i64(~MAKE_64BIT_MASK(15, 1));
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mask = tcg_constant_i64(~MAKE_64BIT_MASK(15, 1));
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tcg_gen_not_i64(rs2, rs2);
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tcg_gen_andc_i64(rs2, rs2, mask);
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tcg_gen_and_i64(dest, mask, rs1);
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@ -201,8 +201,8 @@ static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in)
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*/
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static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
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{
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TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull);
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TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull);
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TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull);
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TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull);
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tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
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}
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