mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/riscv: Avoid tcg_const_*

Browse Source 
All uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-02-26 09:15:34 -10:00
parent a5ea3dd758
commit 2f668fabbc
3 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
target/riscv/insn_trans/trans_rvv.c.inc
View File

@ -209,8 +209,8 @@ static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a)
static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a) static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a)
{ {
TCGv s1 = tcg_const_tl(a->rs1); TCGv s1 = tcg_constant_tl(a->rs1);
TCGv s2 = tcg_const_tl(a->zimm); TCGv s2 = tcg_constant_tl(a->zimm);
return do_vsetivli(s, a->rd, s1, s2); return do_vsetivli(s, a->rd, s1, s2);
} }

2
target/riscv/insn_trans/trans_rvzfh.c.inc
View File

@ -299,7 +299,7 @@ static bool trans_fsgnjn_h(DisasContext *ctx, arg_fsgnjn_h *a)
* Replace bit 15 in rs1 with inverse in rs2. * Replace bit 15 in rs1 with inverse in rs2.
* This formulation retains the nanboxing of rs1. * This formulation retains the nanboxing of rs1.
*/ */
mask = tcg_const_i64(~MAKE_64BIT_MASK(15, 1)); mask = tcg_constant_i64(~MAKE_64BIT_MASK(15, 1));
tcg_gen_not_i64(rs2, rs2); tcg_gen_not_i64(rs2, rs2);
tcg_gen_andc_i64(rs2, rs2, mask); tcg_gen_andc_i64(rs2, rs2, mask);
tcg_gen_and_i64(dest, mask, rs1); tcg_gen_and_i64(dest, mask, rs1);

4
target/riscv/translate.c
View File

@ -201,8 +201,8 @@ static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in)
*/ */
static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
{ {
TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull);
TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull);
tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
} }