sh7750: Change cpu field type to SuperHCPU
This brings us a step closer to QOM'ified SH7750 SoC and
fixes b350ab75 (target-sh4: Move PVR/PRR/CVR into SuperHCPUClass)
assuming SuperHCPU type for SUPERH_CPU_GET_CLASS().
Fix Coding Style issues while at it (indentation, braces).
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Andreas Färber
Aurelien Jarno
parent
06f3ed2698
commit
2f493fee18
@ -258,7 +258,7 @@ static void r2d_init(QEMUMachineInitArgs *args)
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vmstate_register_ram_global(sdram);
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memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
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/* Register peripherals */
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s = sh7750_init(env, address_space_mem);
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s = sh7750_init(cpu, address_space_mem);
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irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
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dev = qdev_create(NULL, "sh_pci");
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@ -44,7 +44,7 @@ typedef struct SH7750State {
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MemoryRegion iomem_ffc;
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MemoryRegion mmct_iomem;
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/* CPU */
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CPUSH4State *cpu;
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SuperHCPU *cpu;
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/* Peripheral frequency in Hz */
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uint32_t periph_freq;
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/* SDRAM controller */
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@ -79,7 +79,7 @@ typedef struct SH7750State {
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static inline int has_bcr3_and_bcr4(SH7750State * s)
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{
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return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4);
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return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4;
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}
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/**********************************************************************
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I/O ports
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@ -271,21 +271,21 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
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ignore_access("long read", addr);
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return 0;
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case SH7750_MMUCR_A7:
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return s->cpu->mmucr;
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return s->cpu->env.mmucr;
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case SH7750_PTEH_A7:
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return s->cpu->pteh;
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return s->cpu->env.pteh;
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case SH7750_PTEL_A7:
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return s->cpu->ptel;
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return s->cpu->env.ptel;
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case SH7750_TTB_A7:
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return s->cpu->ttb;
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return s->cpu->env.ttb;
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case SH7750_TEA_A7:
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return s->cpu->tea;
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return s->cpu->env.tea;
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case SH7750_TRA_A7:
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return s->cpu->tra;
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return s->cpu->env.tra;
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case SH7750_EXPEVT_A7:
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return s->cpu->expevt;
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return s->cpu->env.expevt;
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case SH7750_INTEVT_A7:
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return s->cpu->intevt;
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return s->cpu->env.intevt;
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case SH7750_CCR_A7:
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return s->ccr;
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case 0x1f000030: /* Processor version */
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@ -409,37 +409,38 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr,
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return;
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case SH7750_MMUCR_A7:
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if (mem_value & MMUCR_TI) {
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cpu_sh4_invalidate_tlb(s->cpu);
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cpu_sh4_invalidate_tlb(&s->cpu->env);
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}
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s->cpu->mmucr = mem_value & ~MMUCR_TI;
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s->cpu->env.mmucr = mem_value & ~MMUCR_TI;
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return;
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case SH7750_PTEH_A7:
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/* If asid changes, clear all registered tlb entries. */
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if ((s->cpu->pteh & 0xff) != (mem_value & 0xff))
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tlb_flush(s->cpu, 1);
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s->cpu->pteh = mem_value;
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return;
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if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) {
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tlb_flush(&s->cpu->env, 1);
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}
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s->cpu->env.pteh = mem_value;
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return;
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case SH7750_PTEL_A7:
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s->cpu->ptel = mem_value;
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return;
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s->cpu->env.ptel = mem_value;
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return;
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case SH7750_PTEA_A7:
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s->cpu->ptea = mem_value & 0x0000000f;
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return;
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s->cpu->env.ptea = mem_value & 0x0000000f;
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return;
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case SH7750_TTB_A7:
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s->cpu->ttb = mem_value;
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return;
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s->cpu->env.ttb = mem_value;
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return;
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case SH7750_TEA_A7:
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s->cpu->tea = mem_value;
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return;
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s->cpu->env.tea = mem_value;
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return;
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case SH7750_TRA_A7:
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s->cpu->tra = mem_value & 0x000007ff;
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return;
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s->cpu->env.tra = mem_value & 0x000007ff;
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return;
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case SH7750_EXPEVT_A7:
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s->cpu->expevt = mem_value & 0x000007ff;
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return;
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s->cpu->env.expevt = mem_value & 0x000007ff;
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return;
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case SH7750_INTEVT_A7:
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s->cpu->intevt = mem_value & 0x000007ff;
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return;
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s->cpu->env.intevt = mem_value & 0x000007ff;
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return;
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case SH7750_CCR_A7:
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s->ccr = mem_value;
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return;
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@ -651,20 +652,20 @@ static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr,
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/* do nothing */
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break;
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case MM_ITLB_ADDR:
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ret = cpu_sh4_read_mmaped_itlb_addr(s->cpu, addr);
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ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr);
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break;
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case MM_ITLB_DATA:
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ret = cpu_sh4_read_mmaped_itlb_data(s->cpu, addr);
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ret = cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr);
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break;
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case MM_OCACHE_ADDR:
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case MM_OCACHE_DATA:
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/* do nothing */
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break;
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case MM_UTLB_ADDR:
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ret = cpu_sh4_read_mmaped_utlb_addr(s->cpu, addr);
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ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr);
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break;
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case MM_UTLB_DATA:
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ret = cpu_sh4_read_mmaped_utlb_data(s->cpu, addr);
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ret = cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr);
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break;
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default:
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abort();
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@ -694,10 +695,10 @@ static void sh7750_mmct_write(void *opaque, hwaddr addr,
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/* do nothing */
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break;
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case MM_ITLB_ADDR:
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cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value);
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cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value);
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break;
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case MM_ITLB_DATA:
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cpu_sh4_write_mmaped_itlb_data(s->cpu, addr, mem_value);
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cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value);
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abort();
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break;
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case MM_OCACHE_ADDR:
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@ -705,10 +706,10 @@ static void sh7750_mmct_write(void *opaque, hwaddr addr,
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/* do nothing */
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break;
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case MM_UTLB_ADDR:
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cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value);
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cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value);
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break;
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case MM_UTLB_DATA:
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cpu_sh4_write_mmaped_utlb_data(s->cpu, addr, mem_value);
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cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value);
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break;
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default:
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abort();
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@ -722,7 +723,7 @@ static const MemoryRegionOps sh7750_mmct_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
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SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
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{
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SH7750State *s;
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@ -768,7 +769,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
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_INTC_ARRAY(vectors),
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_INTC_ARRAY(groups));
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cpu->intc_handle = &s->intc;
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cpu->env.intc_handle = &s->intc;
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sh_serial_init(sysmem, 0x1fe00000,
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0, s->periph_freq, serial_hds[0],
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@ -794,19 +795,19 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
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s->intc.irqs[TMU2_TUNI],
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s->intc.irqs[TMU2_TICPI]);
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if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
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if (cpu->env.id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
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sh_intc_register_sources(&s->intc,
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_INTC_ARRAY(vectors_dma4),
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_INTC_ARRAY(groups_dma4));
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}
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if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
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if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
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sh_intc_register_sources(&s->intc,
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_INTC_ARRAY(vectors_dma8),
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_INTC_ARRAY(groups_dma8));
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}
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if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
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if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
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sh_intc_register_sources(&s->intc,
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_INTC_ARRAY(vectors_tmu34),
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NULL, 0);
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@ -816,13 +817,13 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
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NULL, NULL);
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}
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if (cpu->id & (SH_CPU_SH7751_ALL)) {
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if (cpu->env.id & (SH_CPU_SH7751_ALL)) {
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sh_intc_register_sources(&s->intc,
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_INTC_ARRAY(vectors_pci),
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_INTC_ARRAY(groups_pci));
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}
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if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
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if (cpu->env.id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
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sh_intc_register_sources(&s->intc,
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_INTC_ARRAY(vectors_irlm),
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NULL, 0);
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@ -41,7 +41,7 @@ static void shix_init(QEMUMachineInitArgs *args)
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{
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const char *cpu_model = args->cpu_model;
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int ret;
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CPUSH4State *env;
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SuperHCPU *cpu;
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struct SH7750State *s;
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *rom = g_new(MemoryRegion, 1);
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@ -51,8 +51,8 @@ static void shix_init(QEMUMachineInitArgs *args)
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cpu_model = "any";
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printf("Initializing CPU\n");
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env = cpu_init(cpu_model);
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if (env == NULL) {
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cpu = cpu_sh4_init(cpu_model);
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if (cpu == NULL) {
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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@ -85,7 +85,7 @@ static void shix_init(QEMUMachineInitArgs *args)
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}
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/* Register peripherals */
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s = sh7750_init(env, sysmem);
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s = sh7750_init(cpu, sysmem);
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/* XXXXX Check success */
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tc58128_init(s, "shix_linux_nand.bin", NULL);
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fprintf(stderr, "initialization terminated\n");
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@ -11,7 +11,7 @@
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struct SH7750State;
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struct MemoryRegion;
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struct SH7750State *sh7750_init(CPUSH4State * cpu, struct MemoryRegion *sysmem);
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struct SH7750State *sh7750_init(SuperHCPU *cpu, struct MemoryRegion *sysmem);
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typedef struct {
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/* The callback will be triggered if any of the designated lines change */
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