target-alpha: Inline call_pal
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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591243846f
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2f458b7c31
@ -92,7 +92,6 @@ DEF_HELPER_FLAGS_2(ieee_input_s, TCG_CALL_NO_WG, void, env, i64)
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#if !defined (CONFIG_USER_ONLY)
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DEF_HELPER_2(hw_ret, void, env, i64)
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DEF_HELPER_3(call_pal, void, env, i64, i64)
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DEF_HELPER_2(ldl_phys, i64, env, i64)
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DEF_HELPER_2(ldq_phys, i64, env, i64)
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@ -48,14 +48,6 @@ void helper_hw_ret(CPUAlphaState *env, uint64_t a)
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env->pal_mode = a & 1;
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}
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void helper_call_pal(CPUAlphaState *env, uint64_t pc, uint64_t entry_ofs)
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{
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int pal_mode = env->pal_mode;
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env->exc_addr = pc | pal_mode;
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env->pc = env->palbr + entry_ofs;
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env->pal_mode = 1;
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}
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void helper_tbia(CPUAlphaState *env)
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{
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tlb_flush(CPU(alpha_env_get_cpu(env)), 1);
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@ -42,6 +42,9 @@ typedef struct DisasContext DisasContext;
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struct DisasContext {
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struct TranslationBlock *tb;
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uint64_t pc;
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#ifndef CONFIG_USER_ONLY
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uint64_t palbr;
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#endif
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int mem_idx;
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/* Current rounding mode for this TB. */
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@ -1206,15 +1209,24 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
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return gen_excp(ctx, EXCP_CALL_PAL, palcode);
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#else
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{
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TCGv pc = tcg_const_i64(ctx->pc);
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TCGv entry = tcg_const_i64(palcode & 0x80
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? 0x2000 + (palcode - 0x80) * 64
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: 0x1000 + palcode * 64);
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TCGv tmp = tcg_temp_new();
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uint64_t exc_addr = ctx->pc;
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uint64_t entry = ctx->palbr;
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gen_helper_call_pal(cpu_env, pc, entry);
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if (ctx->tb->flags & TB_FLAGS_PAL_MODE) {
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exc_addr |= 1;
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} else {
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tcg_gen_movi_i64(tmp, 1);
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tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, pal_mode));
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}
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tcg_temp_free(entry);
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tcg_temp_free(pc);
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tcg_gen_movi_i64(tmp, exc_addr);
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tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr));
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tcg_temp_free(tmp);
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entry += (palcode & 0x80
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? 0x2000 + (palcode - 0x80) * 64
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: 0x1000 + palcode * 64);
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/* Since the destination is running in PALmode, we don't really
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need the page permissions check. We'll see the existence of
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@ -1222,11 +1234,13 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
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we change the PAL base register. */
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if (!ctx->singlestep_enabled && !(ctx->tb->cflags & CF_LAST_IO)) {
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tcg_gen_goto_tb(0);
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tcg_gen_movi_i64(cpu_pc, entry);
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tcg_gen_exit_tb((uintptr_t)ctx->tb);
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return EXIT_GOTO_TB;
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} else {
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tcg_gen_movi_i64(cpu_pc, entry);
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return EXIT_PC_UPDATED;
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}
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return EXIT_PC_UPDATED;
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}
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#endif
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}
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@ -2861,6 +2875,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
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#ifdef CONFIG_USER_ONLY
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ctx.ir = cpu_std_ir;
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#else
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ctx.palbr = env->palbr;
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ctx.ir = (tb->flags & TB_FLAGS_PAL_MODE ? cpu_pal_ir : cpu_std_ir);
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#endif
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