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target/mips: Convert MSA COPY_U opcode to decodetree

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Convert the COPY_U opcode (Element Copy to GPR Unsigned) to
decodetree.

Since the 'n' field is a constant value, use tcg_constant_i32()
instead of a TCG temporary.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211028210843.2120802-26-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-10-19 17:58:41 +02:00
parent 0a510c934c
commit 2f2745c81a
2 changed files with 41 additions and 26 deletions
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1
target/mips/tcg/msa.decode
View File

@ -167,6 +167,7 @@ BNZ 010001 111 .. ..... ................ @bz
SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df
INSVE 011110 0101 ...... ..... ..... 011001 @elm_df
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf_w

66
target/mips/tcg/msa_translate.c
View File

@ -48,7 +48,6 @@ enum {
OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_COPY_U_df = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
};
@ -592,6 +591,46 @@ TRANS(SLDI, trans_msa_elm, gen_helper_msa_sldi_df);
TRANS(SPLATI, trans_msa_elm, gen_helper_msa_splati_df);
TRANS(INSVE, trans_msa_elm, gen_helper_msa_insve_df);
static bool trans_msa_elm_fn(DisasContext *ctx, arg_msa_elm_df *a,
gen_helper_piii * const gen_msa_elm[4])
{
if (a->df < 0 || !gen_msa_elm[a->df]) {
return false;
}
if (check_msa_enabled(ctx)) {
return true;
}
if (a->wd == 0) {
/* Treat as NOP. */
return true;
}
gen_msa_elm[a->df](cpu_env,
tcg_constant_i32(a->wd),
tcg_constant_i32(a->ws),
tcg_constant_i32(a->n));
return true;
}
#if defined(TARGET_MIPS64)
#define NULL_IF_MIPS32(function) function
#else
#define NULL_IF_MIPS32(function) NULL
#endif
static bool trans_COPY_U(DisasContext *ctx, arg_msa_elm_df *a)
{
static gen_helper_piii * const gen_msa_copy_u[4] = {
gen_helper_msa_copy_u_b, gen_helper_msa_copy_u_h,
NULL_IF_MIPS32(gen_helper_msa_copy_u_w), NULL
};
return trans_msa_elm_fn(ctx, a, gen_msa_copy_u);
}
static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
{
#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
@ -604,7 +643,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
case OPC_COPY_U_df:
case OPC_INSERT_df:
#if !defined(TARGET_MIPS64)
/* Double format valid only for MIPS64 */
@ -612,11 +650,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
gen_reserved_instruction(ctx);
break;
}
if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
(df == DF_WORD)) {
gen_reserved_instruction(ctx);
break;
}
#endif
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
@ -635,25 +668,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
case DF_DOUBLE:
gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
break;
#endif
default:
assert(0);
}
}
break;
case OPC_COPY_U_df:
if (likely(wd != 0)) {
switch (df) {
case DF_BYTE:
gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn);
break;
case DF_HALF:
gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn);
break;
#if defined(TARGET_MIPS64)
case DF_WORD:
gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn);
break;
#endif
default:
assert(0);