target/arm: Move aa32_va_parameters to ptw.c
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-22-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -10771,70 +10771,6 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
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ARMMMUIdx mmu_idx)
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{
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uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
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uint32_t el = regime_el(env, mmu_idx);
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int select, tsz;
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bool epd, hpd;
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assert(mmu_idx != ARMMMUIdx_Stage2_S);
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if (mmu_idx == ARMMMUIdx_Stage2) {
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/* VTCR */
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bool sext = extract32(tcr, 4, 1);
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bool sign = extract32(tcr, 3, 1);
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/*
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* If the sign-extend bit is not the same as t0sz[3], the result
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* is unpredictable. Flag this as a guest error.
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*/
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if (sign != sext) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
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}
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tsz = sextract32(tcr, 0, 4) + 8;
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select = 0;
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hpd = false;
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epd = false;
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} else if (el == 2) {
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/* HTCR */
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tsz = extract32(tcr, 0, 3);
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select = 0;
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hpd = extract64(tcr, 24, 1);
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epd = false;
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} else {
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int t0sz = extract32(tcr, 0, 3);
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int t1sz = extract32(tcr, 16, 3);
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if (t1sz == 0) {
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select = va > (0xffffffffu >> t0sz);
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} else {
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/* Note that we will detect errors later. */
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select = va >= ~(0xffffffffu >> t1sz);
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}
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if (!select) {
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tsz = t0sz;
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epd = extract32(tcr, 7, 1);
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hpd = extract64(tcr, 41, 1);
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} else {
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tsz = t1sz;
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epd = extract32(tcr, 23, 1);
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hpd = extract64(tcr, 42, 1);
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}
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/* For aarch32, hpd0 is not enabled without t2e as well. */
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hpd &= extract32(tcr, 6, 1);
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}
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return (ARMVAParameters) {
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.tsz = tsz,
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.select = select,
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.epd = epd,
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.hpd = hpd,
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};
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}
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hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
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hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
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MemTxAttrs *attrs)
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MemTxAttrs *attrs)
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{
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{
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@ -615,6 +615,70 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
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return prot_rw | PAGE_EXEC;
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return prot_rw | PAGE_EXEC;
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}
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}
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static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
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ARMMMUIdx mmu_idx)
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{
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uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
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uint32_t el = regime_el(env, mmu_idx);
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int select, tsz;
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bool epd, hpd;
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assert(mmu_idx != ARMMMUIdx_Stage2_S);
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if (mmu_idx == ARMMMUIdx_Stage2) {
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/* VTCR */
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bool sext = extract32(tcr, 4, 1);
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bool sign = extract32(tcr, 3, 1);
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/*
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* If the sign-extend bit is not the same as t0sz[3], the result
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* is unpredictable. Flag this as a guest error.
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*/
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if (sign != sext) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
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}
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tsz = sextract32(tcr, 0, 4) + 8;
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select = 0;
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hpd = false;
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epd = false;
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} else if (el == 2) {
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/* HTCR */
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tsz = extract32(tcr, 0, 3);
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select = 0;
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hpd = extract64(tcr, 24, 1);
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epd = false;
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} else {
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int t0sz = extract32(tcr, 0, 3);
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int t1sz = extract32(tcr, 16, 3);
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if (t1sz == 0) {
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select = va > (0xffffffffu >> t0sz);
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} else {
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/* Note that we will detect errors later. */
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select = va >= ~(0xffffffffu >> t1sz);
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}
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if (!select) {
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tsz = t0sz;
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epd = extract32(tcr, 7, 1);
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hpd = extract64(tcr, 41, 1);
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} else {
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tsz = t1sz;
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epd = extract32(tcr, 23, 1);
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hpd = extract64(tcr, 42, 1);
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}
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/* For aarch32, hpd0 is not enabled without t2e as well. */
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hpd &= extract32(tcr, 6, 1);
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}
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return (ARMVAParameters) {
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.tsz = tsz,
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.select = select,
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.epd = epd,
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.hpd = hpd,
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};
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}
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/*
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/*
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* check_s2_mmu_setup
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* check_s2_mmu_setup
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* @cpu: ARMCPU
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* @cpu: ARMCPU
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@ -25,8 +25,5 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
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return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
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return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
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}
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}
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ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
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ARMMMUIdx mmu_idx);
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#endif /* !CONFIG_USER_ONLY */
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#endif /* !CONFIG_USER_ONLY */
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#endif /* TARGET_ARM_PTW_H */
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#endif /* TARGET_ARM_PTW_H */
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