target-arm queue:
* bcm2836: wire up CPU timer interrupts correctly * linux-user: ignore EXCP_YIELD in ARM cpu_loop() * target-arm: correctly reset SCTLR_EL3 * target-arm: remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3 * target-arm: make the 64-bit version of VTCR do the migration -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJXAploAAoJEDwlJe0UNgzeTUsP/AyHEX1mcovDZ9lcaxc+Vgmf LIi71wE8qzc1irp4f02Dmm5/eIX3UYv5n+S8LxL3HAykSYO5wjG30TnPHDnv0wHP BolhHMxh7LU6WTVoP7fjX3OiE9RwzJu8TGAJZrbwdMYeTTSLBP+hTKvM23CS6Dn0 r7LHF6blXeltYHtiPhFkziGtN6YgrSgGUmsunFa7ZAkqxyC7uyfsKkMF7HmYWvcn MwEOYoLNDpVhAdoU4iqz64B3Vl/R0T93c67nBYmCguN/MTXno/rJGvZ8CHeIFydc HAw4csw+268QGs7v4TBR+e0WwXS2dtk77F1sEuN3aTtXjqwskNseM+CMRlZNFRlg bM+FdQHojazrRwnvHBgXYr7HDyqV4El/TOilOYdIAdGo9kEzY/1OPjma66TqGkKy ZdhwFtCKMsI7rKqr65rFINa9lMD8BDdSZhzEgGv3O8yOQDLLoPIqQ8z6vnOxsOml QvKxpduQp/7pY+nkYpk9TL3AX4y0sGz4iz9hC4RrSAlOaiBpTpx2vfTi87E6kOCb 6hLFOlUVkY+3i1/M1JUwUhesXXdGzalz/WLRXC6WnwyS8rD5PPHM3k2ndUs5xkSl bCsygk54UyngFGJcNS97BLIWhOF7CfQ0JuLA1+BwL/f0PMDfHhCPOXAe0HQBxu0L sNr/M6Jcl2NqLdXsij5P =8xY7 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160404' into staging target-arm queue: * bcm2836: wire up CPU timer interrupts correctly * linux-user: ignore EXCP_YIELD in ARM cpu_loop() * target-arm: correctly reset SCTLR_EL3 * target-arm: remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3 * target-arm: make the 64-bit version of VTCR do the migration # gpg: Signature made Mon 04 Apr 2016 17:42:16 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-target-arm-20160404: target-arm: Make the 64-bit version of VTCR do the migration target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3 target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUs linux-user: arm: Handle (ignore) EXCP_YIELD in ARM cpu_loop() hw/arm/bcm2836: Wire up CPU timer interrupts correctly Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
2e3a76ae3e
@ -139,9 +139,13 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
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/* Connect timers from the CPU to the interrupt controller */
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qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_PHYS,
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qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n));
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qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n));
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qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_VIRT,
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qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n));
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qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_HYP,
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qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n));
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qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_SEC,
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qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n));
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}
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}
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@ -907,6 +907,9 @@ void cpu_loop(CPUARMState *env)
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if (do_kernel_trap(env))
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goto error;
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break;
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case EXCP_YIELD:
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/* nothing to do here for user-mode, just resume guest code */
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break;
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default:
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error:
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EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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@ -1097,6 +1100,9 @@ void cpu_loop(CPUARMState *env)
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case EXCP_SEMIHOST:
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env->xregs[0] = do_arm_semihosting(env);
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break;
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case EXCP_YIELD:
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/* nothing to do here for user-mode, just resume guest code */
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break;
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default:
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EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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abort();
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@ -3509,7 +3509,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
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.access = PL2_RW,
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.fieldoffset = offsetof(CPUARMState, elr_el[2]) },
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{ .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
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.type = ARM_CP_ALIAS,
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.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
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.access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
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{ .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
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@ -3565,11 +3564,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
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.fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
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{ .name = "VTCR", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
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.type = ARM_CP_ALIAS,
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.access = PL2_RW, .accessfn = access_el3_aa32ns,
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.fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
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{ .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
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.access = PL2_RW, .type = ARM_CP_ALIAS,
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.access = PL2_RW,
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/* no .writefn needed as this can't cause an ASID change;
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* no .raw_writefn or .resetfn needed as we never use mask/base_mask
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*/
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.fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
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{ .name = "VTTBR", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 6, .crm = 2,
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@ -3744,11 +3747,6 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
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.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
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.writefn = vbar_write, .resetvalue = 0,
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.fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
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{ .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
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.type = ARM_CP_ALIAS, /* reset handled by AArch32 view */
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.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
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.access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
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.fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
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{ .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
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.access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
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@ -3764,7 +3762,6 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
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.access = PL3_RW,
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.fieldoffset = offsetof(CPUARMState, elr_el[3]) },
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{ .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
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.type = ARM_CP_ALIAS,
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.opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
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.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
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{ .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
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@ -4641,12 +4638,20 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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}
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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define_arm_cp_regs(cpu, el3_cp_reginfo);
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ARMCPRegInfo rvbar = {
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.name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
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.type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar
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ARMCPRegInfo el3_regs[] = {
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{ .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
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.type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
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{ .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
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.access = PL3_RW,
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.raw_writefn = raw_write, .writefn = sctlr_write,
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.fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
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.resetvalue = cpu->reset_sctlr },
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REGINFO_SENTINEL
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};
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define_one_arm_cp_reg(cpu, &rvbar);
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define_arm_cp_regs(cpu, el3_regs);
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}
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/* The behaviour of NSACR is sufficiently various that we don't
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* try to describe it in a single reginfo:
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