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target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI

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Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or
CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With
CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-9-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jinjie Ruan 2024-04-19 14:32:59 +01:00 committed by Peter Maydell
parent 963e4e3648
commit 2e0be5f6b1
2 changed files with 15 additions and 0 deletions
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2
target/arm/cpu.h
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@ -1398,6 +1398,8 @@ void pmu_init(ARMCPU *cpu);
#define CPSR_N (1U << 31) #define CPSR_N (1U << 31)
#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
#define ISR_FS (1U << 9)
#define ISR_IS (1U << 10)
#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \

13
target/arm/helper.c
View File

@ -2021,16 +2021,29 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
ret |= CPSR_I; ret |= CPSR_I;
} }
if (cs->interrupt_request & CPU_INTERRUPT_VINMI) {
ret |= ISR_IS;
ret |= CPSR_I;
}
} else { } else {
if (cs->interrupt_request & CPU_INTERRUPT_HARD) { if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
ret |= CPSR_I; ret |= CPSR_I;
} }
if (cs->interrupt_request & CPU_INTERRUPT_NMI) {
ret |= ISR_IS;
ret |= CPSR_I;
}
} }
if (hcr_el2 & HCR_FMO) { if (hcr_el2 & HCR_FMO) {
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
ret |= CPSR_F; ret |= CPSR_F;
} }
if (cs->interrupt_request & CPU_INTERRUPT_VFNMI) {
ret |= ISR_FS;
ret |= CPSR_F;
}
} else { } else {
if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
ret |= CPSR_F; ret |= CPSR_F;