tcg/s390x: Implement tcg_out_ld/st for vector types
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -265,6 +265,12 @@ typedef enum S390Opcode {
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RX_STC = 0x42,
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RX_STH = 0x40,
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VRX_VL = 0xe706,
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VRX_VLLEZ = 0xe704,
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VRX_VST = 0xe70e,
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VRX_VSTEF = 0xe70b,
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VRX_VSTEG = 0xe70a,
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NOP = 0x0707,
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} S390Opcode;
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@ -412,6 +418,16 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
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static const tcg_insn_unit *tb_ret_addr;
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uint64_t s390_facilities[3];
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static inline bool is_general_reg(TCGReg r)
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{
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return r <= TCG_REG_R15;
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}
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static inline bool is_vector_reg(TCGReg r)
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{
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return r >= TCG_REG_V0 && r <= TCG_REG_V31;
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}
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static bool patch_reloc(tcg_insn_unit *src_rw, int type,
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intptr_t value, intptr_t addend)
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{
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@ -529,6 +545,31 @@ static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1,
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#define tcg_out_insn_RX tcg_out_insn_RS
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#define tcg_out_insn_RXY tcg_out_insn_RSY
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static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
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{
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/*
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* Shift bit 4 of each regno to its corresponding bit of RXB.
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* RXB itself begins at bit 8 of the instruction so 8 - 4 = 4
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* is the left-shift of the 4th operand.
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*/
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return ((v1 & 0x10) << (4 + 3))
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| ((v2 & 0x10) << (4 + 2))
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| ((v3 & 0x10) << (4 + 1))
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| ((v4 & 0x10) << (4 + 0));
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}
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static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1,
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TCGReg b2, TCGReg x2, intptr_t d2, int m3)
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{
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tcg_debug_assert(is_vector_reg(v1));
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tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
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tcg_debug_assert(is_general_reg(x2));
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tcg_debug_assert(is_general_reg(b2));
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tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | x2);
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tcg_out16(s, (b2 << 12) | d2);
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tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12));
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}
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/* Emit an opcode with "type-checking" of the format. */
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#define tcg_out_insn(S, FMT, OP, ...) \
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glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__)
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@ -705,25 +746,92 @@ static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy,
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}
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}
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static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx,
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TCGReg data, TCGReg base, TCGReg index,
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tcg_target_long ofs, int m3)
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{
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if (ofs < 0 || ofs >= 0x1000) {
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if (ofs >= -0x80000 && ofs < 0x80000) {
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tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs);
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base = TCG_TMP0;
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index = TCG_REG_NONE;
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ofs = 0;
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} else {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs);
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if (index != TCG_REG_NONE) {
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tcg_out_insn(s, RRE, AGR, TCG_TMP0, index);
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}
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index = TCG_TMP0;
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ofs = 0;
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}
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}
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tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3);
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}
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/* load data without address translation or endianness conversion */
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static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
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TCGReg base, intptr_t ofs)
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static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
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TCGReg base, intptr_t ofs)
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{
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if (type == TCG_TYPE_I32) {
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tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs);
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} else {
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tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs);
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switch (type) {
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case TCG_TYPE_I32:
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if (likely(is_general_reg(data))) {
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tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs);
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break;
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}
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tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32);
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break;
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case TCG_TYPE_I64:
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if (likely(is_general_reg(data))) {
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tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs);
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break;
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}
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/* fallthru */
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case TCG_TYPE_V64:
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tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64);
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break;
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case TCG_TYPE_V128:
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/* Hint quadword aligned. */
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tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4);
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break;
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default:
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g_assert_not_reached();
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}
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}
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static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
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TCGReg base, intptr_t ofs)
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static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
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TCGReg base, intptr_t ofs)
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{
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if (type == TCG_TYPE_I32) {
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tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs);
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} else {
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tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs);
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switch (type) {
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case TCG_TYPE_I32:
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if (likely(is_general_reg(data))) {
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tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs);
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} else {
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tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1);
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}
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break;
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case TCG_TYPE_I64:
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if (likely(is_general_reg(data))) {
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tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs);
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break;
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}
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/* fallthru */
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case TCG_TYPE_V64:
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tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0);
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break;
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case TCG_TYPE_V128:
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/* Hint quadword aligned. */
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tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4);
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break;
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default:
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g_assert_not_reached();
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}
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}
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