hw/omap2.c : separate spi module
Signed-off-by: cmchao <cmchao@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
cmchao
Aurelien Jarno
parent
7f132a21fc
commit
2d08cc7c3f
@ -269,7 +269,7 @@ obj-arm-y += pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o
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obj-arm-y += gumstix.o
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obj-arm-y += zaurus.o ide/microdrive.o spitz.o tosa.o tc6393xb.o
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obj-arm-y += omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o omap_gpio.o omap_intc.o
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obj-arm-y += omap2.o omap_dss.o soc_dma.o omap_gptimer.o omap_synctimer.o omap_gpmc.o omap_sdrc.o
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obj-arm-y += omap2.o omap_dss.o soc_dma.o omap_gptimer.o omap_synctimer.o omap_gpmc.o omap_sdrc.o omap_spi.o
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obj-arm-y += omap_sx1.o palm.o tsc210x.o
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obj-arm-y += nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o
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obj-arm-y += mst_fpga.o mainstone.o
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@ -706,12 +706,14 @@ struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
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void omap_uwire_attach(struct omap_uwire_s *s,
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uWireSlave *slave, int chipselect);
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/* OMAP2 spi */
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struct omap_mcspi_s;
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struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
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qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
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void omap_mcspi_attach(struct omap_mcspi_s *s,
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uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
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int chipselect);
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void omap_mcspi_reset(struct omap_mcspi_s *s);
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struct omap_rtc_s;
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struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
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323
hw/omap2.c
323
hw/omap2.c
@ -29,329 +29,6 @@
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#include "soc_dma.h"
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#include "audio/audio.h"
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/* Multichannel SPI */
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struct omap_mcspi_s {
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qemu_irq irq;
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int chnum;
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uint32_t sysconfig;
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uint32_t systest;
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uint32_t irqst;
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uint32_t irqen;
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uint32_t wken;
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uint32_t control;
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struct omap_mcspi_ch_s {
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qemu_irq txdrq;
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qemu_irq rxdrq;
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uint32_t (*txrx)(void *opaque, uint32_t, int);
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void *opaque;
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uint32_t tx;
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uint32_t rx;
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uint32_t config;
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uint32_t status;
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uint32_t control;
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} ch[4];
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};
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static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
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{
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qemu_set_irq(s->irq, s->irqst & s->irqen);
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}
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static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
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{
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qemu_set_irq(ch->txdrq,
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(ch->control & 1) && /* EN */
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(ch->config & (1 << 14)) && /* DMAW */
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(ch->status & (1 << 1)) && /* TXS */
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((ch->config >> 12) & 3) != 1); /* TRM */
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qemu_set_irq(ch->rxdrq,
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(ch->control & 1) && /* EN */
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(ch->config & (1 << 15)) && /* DMAW */
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(ch->status & (1 << 0)) && /* RXS */
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((ch->config >> 12) & 3) != 2); /* TRM */
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}
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static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
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{
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struct omap_mcspi_ch_s *ch = s->ch + chnum;
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if (!(ch->control & 1)) /* EN */
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return;
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if ((ch->status & (1 << 0)) && /* RXS */
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((ch->config >> 12) & 3) != 2 && /* TRM */
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!(ch->config & (1 << 19))) /* TURBO */
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goto intr_update;
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if ((ch->status & (1 << 1)) && /* TXS */
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((ch->config >> 12) & 3) != 1) /* TRM */
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goto intr_update;
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if (!(s->control & 1) || /* SINGLE */
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(ch->config & (1 << 20))) { /* FORCE */
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if (ch->txrx)
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ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
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1 + (0x1f & (ch->config >> 7)));
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}
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ch->tx = 0;
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ch->status |= 1 << 2; /* EOT */
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ch->status |= 1 << 1; /* TXS */
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if (((ch->config >> 12) & 3) != 2) /* TRM */
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ch->status |= 1 << 0; /* RXS */
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intr_update:
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if ((ch->status & (1 << 0)) && /* RXS */
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((ch->config >> 12) & 3) != 2 && /* TRM */
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!(ch->config & (1 << 19))) /* TURBO */
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s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */
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if ((ch->status & (1 << 1)) && /* TXS */
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((ch->config >> 12) & 3) != 1) /* TRM */
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s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */
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omap_mcspi_interrupt_update(s);
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omap_mcspi_dmarequest_update(ch);
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}
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static void omap_mcspi_reset(struct omap_mcspi_s *s)
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{
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int ch;
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s->sysconfig = 0;
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s->systest = 0;
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s->irqst = 0;
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s->irqen = 0;
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s->wken = 0;
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s->control = 4;
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for (ch = 0; ch < 4; ch ++) {
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s->ch[ch].config = 0x060000;
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s->ch[ch].status = 2; /* TXS */
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s->ch[ch].control = 0;
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omap_mcspi_dmarequest_update(s->ch + ch);
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}
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omap_mcspi_interrupt_update(s);
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}
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static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
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{
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struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
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int ch = 0;
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uint32_t ret;
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switch (addr) {
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case 0x00: /* MCSPI_REVISION */
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return 0x91;
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case 0x10: /* MCSPI_SYSCONFIG */
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return s->sysconfig;
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case 0x14: /* MCSPI_SYSSTATUS */
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return 1; /* RESETDONE */
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case 0x18: /* MCSPI_IRQSTATUS */
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return s->irqst;
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case 0x1c: /* MCSPI_IRQENABLE */
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return s->irqen;
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case 0x20: /* MCSPI_WAKEUPENABLE */
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return s->wken;
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case 0x24: /* MCSPI_SYST */
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return s->systest;
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case 0x28: /* MCSPI_MODULCTRL */
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return s->control;
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case 0x68: ch ++;
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case 0x54: ch ++;
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case 0x40: ch ++;
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case 0x2c: /* MCSPI_CHCONF */
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return s->ch[ch].config;
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case 0x6c: ch ++;
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case 0x58: ch ++;
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case 0x44: ch ++;
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case 0x30: /* MCSPI_CHSTAT */
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return s->ch[ch].status;
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case 0x70: ch ++;
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case 0x5c: ch ++;
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case 0x48: ch ++;
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case 0x34: /* MCSPI_CHCTRL */
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return s->ch[ch].control;
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case 0x74: ch ++;
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case 0x60: ch ++;
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case 0x4c: ch ++;
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case 0x38: /* MCSPI_TX */
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return s->ch[ch].tx;
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case 0x78: ch ++;
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case 0x64: ch ++;
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case 0x50: ch ++;
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case 0x3c: /* MCSPI_RX */
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s->ch[ch].status &= ~(1 << 0); /* RXS */
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ret = s->ch[ch].rx;
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omap_mcspi_transfer_run(s, ch);
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return ret;
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
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int ch = 0;
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switch (addr) {
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case 0x00: /* MCSPI_REVISION */
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case 0x14: /* MCSPI_SYSSTATUS */
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case 0x30: /* MCSPI_CHSTAT0 */
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case 0x3c: /* MCSPI_RX0 */
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case 0x44: /* MCSPI_CHSTAT1 */
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case 0x50: /* MCSPI_RX1 */
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case 0x58: /* MCSPI_CHSTAT2 */
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case 0x64: /* MCSPI_RX2 */
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case 0x6c: /* MCSPI_CHSTAT3 */
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case 0x78: /* MCSPI_RX3 */
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OMAP_RO_REG(addr);
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return;
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case 0x10: /* MCSPI_SYSCONFIG */
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if (value & (1 << 1)) /* SOFTRESET */
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omap_mcspi_reset(s);
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s->sysconfig = value & 0x31d;
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break;
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case 0x18: /* MCSPI_IRQSTATUS */
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if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
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s->irqst &= ~value;
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omap_mcspi_interrupt_update(s);
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}
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break;
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case 0x1c: /* MCSPI_IRQENABLE */
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s->irqen = value & 0x1777f;
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omap_mcspi_interrupt_update(s);
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break;
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case 0x20: /* MCSPI_WAKEUPENABLE */
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s->wken = value & 1;
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break;
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case 0x24: /* MCSPI_SYST */
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if (s->control & (1 << 3)) /* SYSTEM_TEST */
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if (value & (1 << 11)) { /* SSB */
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s->irqst |= 0x1777f;
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omap_mcspi_interrupt_update(s);
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}
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s->systest = value & 0xfff;
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break;
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case 0x28: /* MCSPI_MODULCTRL */
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if (value & (1 << 3)) /* SYSTEM_TEST */
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if (s->systest & (1 << 11)) { /* SSB */
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s->irqst |= 0x1777f;
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omap_mcspi_interrupt_update(s);
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}
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s->control = value & 0xf;
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break;
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case 0x68: ch ++;
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case 0x54: ch ++;
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case 0x40: ch ++;
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case 0x2c: /* MCSPI_CHCONF */
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if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */
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omap_mcspi_dmarequest_update(s->ch + ch);
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if (((value >> 12) & 3) == 3) /* TRM */
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fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
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if (((value >> 7) & 0x1f) < 3) /* WL */
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fprintf(stderr, "%s: invalid WL value (%i)\n",
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__FUNCTION__, (value >> 7) & 0x1f);
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s->ch[ch].config = value & 0x7fffff;
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break;
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case 0x70: ch ++;
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case 0x5c: ch ++;
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case 0x48: ch ++;
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case 0x34: /* MCSPI_CHCTRL */
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if (value & ~s->ch[ch].control & 1) { /* EN */
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s->ch[ch].control |= 1;
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omap_mcspi_transfer_run(s, ch);
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} else
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s->ch[ch].control = value & 1;
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break;
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case 0x74: ch ++;
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case 0x60: ch ++;
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case 0x4c: ch ++;
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case 0x38: /* MCSPI_TX */
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s->ch[ch].tx = value;
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s->ch[ch].status &= ~(1 << 1); /* TXS */
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omap_mcspi_transfer_run(s, ch);
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break;
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default:
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OMAP_BAD_REG(addr);
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return;
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}
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}
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static CPUReadMemoryFunc * const omap_mcspi_readfn[] = {
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omap_badwidth_read32,
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omap_badwidth_read32,
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omap_mcspi_read,
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};
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static CPUWriteMemoryFunc * const omap_mcspi_writefn[] = {
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omap_badwidth_write32,
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omap_badwidth_write32,
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omap_mcspi_write,
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};
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struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
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qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
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{
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int iomemtype;
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struct omap_mcspi_s *s = (struct omap_mcspi_s *)
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qemu_mallocz(sizeof(struct omap_mcspi_s));
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struct omap_mcspi_ch_s *ch = s->ch;
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s->irq = irq;
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s->chnum = chnum;
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while (chnum --) {
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ch->txdrq = *drq ++;
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ch->rxdrq = *drq ++;
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ch ++;
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}
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omap_mcspi_reset(s);
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iomemtype = l4_register_io_memory(omap_mcspi_readfn,
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omap_mcspi_writefn, s);
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omap_l4_attach(ta, 0, iomemtype);
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return s;
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}
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void omap_mcspi_attach(struct omap_mcspi_s *s,
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uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
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int chipselect)
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{
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if (chipselect < 0 || chipselect >= s->chnum)
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hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
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s->ch[chipselect].txrx = txrx;
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s->ch[chipselect].opaque = opaque;
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}
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/* Enhanced Audio Controller (CODEC only) */
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struct omap_eac_s {
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qemu_irq irq;
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346
hw/omap_spi.c
Normal file
346
hw/omap_spi.c
Normal file
@ -0,0 +1,346 @@
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/*
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* TI OMAP processor's Multichannel SPI emulation.
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*
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* Copyright (C) 2007-2009 Nokia Corporation
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*
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* Original code for OMAP2 by Andrzej Zaborowski <andrew@openedhand.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) any later version of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "hw.h"
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#include "omap.h"
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/* Multichannel SPI */
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struct omap_mcspi_s {
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qemu_irq irq;
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int chnum;
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uint32_t sysconfig;
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uint32_t systest;
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uint32_t irqst;
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uint32_t irqen;
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uint32_t wken;
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uint32_t control;
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struct omap_mcspi_ch_s {
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qemu_irq txdrq;
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qemu_irq rxdrq;
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uint32_t (*txrx)(void *opaque, uint32_t, int);
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void *opaque;
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uint32_t tx;
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uint32_t rx;
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uint32_t config;
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uint32_t status;
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uint32_t control;
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} ch[4];
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};
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static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
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{
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qemu_set_irq(s->irq, s->irqst & s->irqen);
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}
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static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
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{
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qemu_set_irq(ch->txdrq,
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(ch->control & 1) && /* EN */
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(ch->config & (1 << 14)) && /* DMAW */
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(ch->status & (1 << 1)) && /* TXS */
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((ch->config >> 12) & 3) != 1); /* TRM */
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qemu_set_irq(ch->rxdrq,
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(ch->control & 1) && /* EN */
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(ch->config & (1 << 15)) && /* DMAW */
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(ch->status & (1 << 0)) && /* RXS */
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((ch->config >> 12) & 3) != 2); /* TRM */
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}
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static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
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{
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struct omap_mcspi_ch_s *ch = s->ch + chnum;
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if (!(ch->control & 1)) /* EN */
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return;
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if ((ch->status & (1 << 0)) && /* RXS */
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((ch->config >> 12) & 3) != 2 && /* TRM */
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!(ch->config & (1 << 19))) /* TURBO */
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goto intr_update;
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if ((ch->status & (1 << 1)) && /* TXS */
|
||||
((ch->config >> 12) & 3) != 1) /* TRM */
|
||||
goto intr_update;
|
||||
|
||||
if (!(s->control & 1) || /* SINGLE */
|
||||
(ch->config & (1 << 20))) { /* FORCE */
|
||||
if (ch->txrx)
|
||||
ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
|
||||
1 + (0x1f & (ch->config >> 7)));
|
||||
}
|
||||
|
||||
ch->tx = 0;
|
||||
ch->status |= 1 << 2; /* EOT */
|
||||
ch->status |= 1 << 1; /* TXS */
|
||||
if (((ch->config >> 12) & 3) != 2) /* TRM */
|
||||
ch->status |= 1 << 0; /* RXS */
|
||||
|
||||
intr_update:
|
||||
if ((ch->status & (1 << 0)) && /* RXS */
|
||||
((ch->config >> 12) & 3) != 2 && /* TRM */
|
||||
!(ch->config & (1 << 19))) /* TURBO */
|
||||
s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */
|
||||
if ((ch->status & (1 << 1)) && /* TXS */
|
||||
((ch->config >> 12) & 3) != 1) /* TRM */
|
||||
s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */
|
||||
omap_mcspi_interrupt_update(s);
|
||||
omap_mcspi_dmarequest_update(ch);
|
||||
}
|
||||
|
||||
void omap_mcspi_reset(struct omap_mcspi_s *s)
|
||||
{
|
||||
int ch;
|
||||
|
||||
s->sysconfig = 0;
|
||||
s->systest = 0;
|
||||
s->irqst = 0;
|
||||
s->irqen = 0;
|
||||
s->wken = 0;
|
||||
s->control = 4;
|
||||
|
||||
for (ch = 0; ch < 4; ch ++) {
|
||||
s->ch[ch].config = 0x060000;
|
||||
s->ch[ch].status = 2; /* TXS */
|
||||
s->ch[ch].control = 0;
|
||||
|
||||
omap_mcspi_dmarequest_update(s->ch + ch);
|
||||
}
|
||||
|
||||
omap_mcspi_interrupt_update(s);
|
||||
}
|
||||
|
||||
static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
|
||||
int ch = 0;
|
||||
uint32_t ret;
|
||||
|
||||
switch (addr) {
|
||||
case 0x00: /* MCSPI_REVISION */
|
||||
return 0x91;
|
||||
|
||||
case 0x10: /* MCSPI_SYSCONFIG */
|
||||
return s->sysconfig;
|
||||
|
||||
case 0x14: /* MCSPI_SYSSTATUS */
|
||||
return 1; /* RESETDONE */
|
||||
|
||||
case 0x18: /* MCSPI_IRQSTATUS */
|
||||
return s->irqst;
|
||||
|
||||
case 0x1c: /* MCSPI_IRQENABLE */
|
||||
return s->irqen;
|
||||
|
||||
case 0x20: /* MCSPI_WAKEUPENABLE */
|
||||
return s->wken;
|
||||
|
||||
case 0x24: /* MCSPI_SYST */
|
||||
return s->systest;
|
||||
|
||||
case 0x28: /* MCSPI_MODULCTRL */
|
||||
return s->control;
|
||||
|
||||
case 0x68: ch ++;
|
||||
case 0x54: ch ++;
|
||||
case 0x40: ch ++;
|
||||
case 0x2c: /* MCSPI_CHCONF */
|
||||
return s->ch[ch].config;
|
||||
|
||||
case 0x6c: ch ++;
|
||||
case 0x58: ch ++;
|
||||
case 0x44: ch ++;
|
||||
case 0x30: /* MCSPI_CHSTAT */
|
||||
return s->ch[ch].status;
|
||||
|
||||
case 0x70: ch ++;
|
||||
case 0x5c: ch ++;
|
||||
case 0x48: ch ++;
|
||||
case 0x34: /* MCSPI_CHCTRL */
|
||||
return s->ch[ch].control;
|
||||
|
||||
case 0x74: ch ++;
|
||||
case 0x60: ch ++;
|
||||
case 0x4c: ch ++;
|
||||
case 0x38: /* MCSPI_TX */
|
||||
return s->ch[ch].tx;
|
||||
|
||||
case 0x78: ch ++;
|
||||
case 0x64: ch ++;
|
||||
case 0x50: ch ++;
|
||||
case 0x3c: /* MCSPI_RX */
|
||||
s->ch[ch].status &= ~(1 << 0); /* RXS */
|
||||
ret = s->ch[ch].rx;
|
||||
omap_mcspi_transfer_run(s, ch);
|
||||
return ret;
|
||||
}
|
||||
|
||||
OMAP_BAD_REG(addr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
|
||||
uint32_t value)
|
||||
{
|
||||
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
|
||||
int ch = 0;
|
||||
|
||||
switch (addr) {
|
||||
case 0x00: /* MCSPI_REVISION */
|
||||
case 0x14: /* MCSPI_SYSSTATUS */
|
||||
case 0x30: /* MCSPI_CHSTAT0 */
|
||||
case 0x3c: /* MCSPI_RX0 */
|
||||
case 0x44: /* MCSPI_CHSTAT1 */
|
||||
case 0x50: /* MCSPI_RX1 */
|
||||
case 0x58: /* MCSPI_CHSTAT2 */
|
||||
case 0x64: /* MCSPI_RX2 */
|
||||
case 0x6c: /* MCSPI_CHSTAT3 */
|
||||
case 0x78: /* MCSPI_RX3 */
|
||||
OMAP_RO_REG(addr);
|
||||
return;
|
||||
|
||||
case 0x10: /* MCSPI_SYSCONFIG */
|
||||
if (value & (1 << 1)) /* SOFTRESET */
|
||||
omap_mcspi_reset(s);
|
||||
s->sysconfig = value & 0x31d;
|
||||
break;
|
||||
|
||||
case 0x18: /* MCSPI_IRQSTATUS */
|
||||
if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
|
||||
s->irqst &= ~value;
|
||||
omap_mcspi_interrupt_update(s);
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x1c: /* MCSPI_IRQENABLE */
|
||||
s->irqen = value & 0x1777f;
|
||||
omap_mcspi_interrupt_update(s);
|
||||
break;
|
||||
|
||||
case 0x20: /* MCSPI_WAKEUPENABLE */
|
||||
s->wken = value & 1;
|
||||
break;
|
||||
|
||||
case 0x24: /* MCSPI_SYST */
|
||||
if (s->control & (1 << 3)) /* SYSTEM_TEST */
|
||||
if (value & (1 << 11)) { /* SSB */
|
||||
s->irqst |= 0x1777f;
|
||||
omap_mcspi_interrupt_update(s);
|
||||
}
|
||||
s->systest = value & 0xfff;
|
||||
break;
|
||||
|
||||
case 0x28: /* MCSPI_MODULCTRL */
|
||||
if (value & (1 << 3)) /* SYSTEM_TEST */
|
||||
if (s->systest & (1 << 11)) { /* SSB */
|
||||
s->irqst |= 0x1777f;
|
||||
omap_mcspi_interrupt_update(s);
|
||||
}
|
||||
s->control = value & 0xf;
|
||||
break;
|
||||
|
||||
case 0x68: ch ++;
|
||||
case 0x54: ch ++;
|
||||
case 0x40: ch ++;
|
||||
case 0x2c: /* MCSPI_CHCONF */
|
||||
if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */
|
||||
omap_mcspi_dmarequest_update(s->ch + ch);
|
||||
if (((value >> 12) & 3) == 3) /* TRM */
|
||||
fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
|
||||
if (((value >> 7) & 0x1f) < 3) /* WL */
|
||||
fprintf(stderr, "%s: invalid WL value (%i)\n",
|
||||
__FUNCTION__, (value >> 7) & 0x1f);
|
||||
s->ch[ch].config = value & 0x7fffff;
|
||||
break;
|
||||
|
||||
case 0x70: ch ++;
|
||||
case 0x5c: ch ++;
|
||||
case 0x48: ch ++;
|
||||
case 0x34: /* MCSPI_CHCTRL */
|
||||
if (value & ~s->ch[ch].control & 1) { /* EN */
|
||||
s->ch[ch].control |= 1;
|
||||
omap_mcspi_transfer_run(s, ch);
|
||||
} else
|
||||
s->ch[ch].control = value & 1;
|
||||
break;
|
||||
|
||||
case 0x74: ch ++;
|
||||
case 0x60: ch ++;
|
||||
case 0x4c: ch ++;
|
||||
case 0x38: /* MCSPI_TX */
|
||||
s->ch[ch].tx = value;
|
||||
s->ch[ch].status &= ~(1 << 1); /* TXS */
|
||||
omap_mcspi_transfer_run(s, ch);
|
||||
break;
|
||||
|
||||
default:
|
||||
OMAP_BAD_REG(addr);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
static CPUReadMemoryFunc * const omap_mcspi_readfn[] = {
|
||||
omap_badwidth_read32,
|
||||
omap_badwidth_read32,
|
||||
omap_mcspi_read,
|
||||
};
|
||||
|
||||
static CPUWriteMemoryFunc * const omap_mcspi_writefn[] = {
|
||||
omap_badwidth_write32,
|
||||
omap_badwidth_write32,
|
||||
omap_mcspi_write,
|
||||
};
|
||||
|
||||
struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
|
||||
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
|
||||
{
|
||||
int iomemtype;
|
||||
struct omap_mcspi_s *s = (struct omap_mcspi_s *)
|
||||
qemu_mallocz(sizeof(struct omap_mcspi_s));
|
||||
struct omap_mcspi_ch_s *ch = s->ch;
|
||||
|
||||
s->irq = irq;
|
||||
s->chnum = chnum;
|
||||
while (chnum --) {
|
||||
ch->txdrq = *drq ++;
|
||||
ch->rxdrq = *drq ++;
|
||||
ch ++;
|
||||
}
|
||||
omap_mcspi_reset(s);
|
||||
|
||||
iomemtype = l4_register_io_memory(omap_mcspi_readfn,
|
||||
omap_mcspi_writefn, s);
|
||||
omap_l4_attach(ta, 0, iomemtype);
|
||||
|
||||
return s;
|
||||
}
|
||||
|
||||
void omap_mcspi_attach(struct omap_mcspi_s *s,
|
||||
uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
|
||||
int chipselect)
|
||||
{
|
||||
if (chipselect < 0 || chipselect >= s->chnum)
|
||||
hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
|
||||
|
||||
s->ch[chipselect].txrx = txrx;
|
||||
s->ch[chipselect].opaque = opaque;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user