tcg/arm: Use tcg_use_softmmu
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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23088ca0bc
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2c53bdf110
@ -89,9 +89,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
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#define TCG_REG_TMP TCG_REG_R12
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#define TCG_VEC_TMP TCG_REG_Q15
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#ifndef CONFIG_SOFTMMU
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#define TCG_REG_GUEST_BASE TCG_REG_R11
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#endif
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typedef enum {
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COND_EQ = 0x0,
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@ -356,14 +354,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
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* r0-r3 will be overwritten when reading the tlb entry (system-mode only);
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* r14 will be overwritten by the BLNE branching to the slow path.
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*/
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#ifdef CONFIG_SOFTMMU
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#define ALL_QLDST_REGS \
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(ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \
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(1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \
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(1 << TCG_REG_R14)))
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#else
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#define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R14))
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#endif
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(ALL_GENERAL_REGS & ~((tcg_use_softmmu ? 0xf : 0) | (1 << TCG_REG_R14)))
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/*
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* ARM immediates for ALU instructions are made of an unsigned 8-bit
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@ -1387,113 +1379,115 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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MemOp opc = get_memop(oi);
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unsigned a_mask;
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#ifdef CONFIG_SOFTMMU
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*h = (HostAddress){
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.cond = COND_AL,
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.base = addrlo,
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.index = TCG_REG_R1,
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.index_scratch = true,
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};
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#else
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*h = (HostAddress){
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.cond = COND_AL,
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.base = addrlo,
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.index = guest_base ? TCG_REG_GUEST_BASE : -1,
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.index_scratch = false,
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};
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#endif
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if (tcg_use_softmmu) {
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*h = (HostAddress){
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.cond = COND_AL,
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.base = addrlo,
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.index = TCG_REG_R1,
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.index_scratch = true,
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};
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} else {
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*h = (HostAddress){
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.cond = COND_AL,
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.base = addrlo,
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.index = guest_base ? TCG_REG_GUEST_BASE : -1,
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.index_scratch = false,
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};
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}
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h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
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a_mask = (1 << h->aa.align) - 1;
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#ifdef CONFIG_SOFTMMU
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int mem_index = get_mmuidx(oi);
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int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write);
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int fast_off = tlb_mask_table_ofs(s, mem_index);
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unsigned s_mask = (1 << (opc & MO_SIZE)) - 1;
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TCGReg t_addr;
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if (tcg_use_softmmu) {
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int mem_index = get_mmuidx(oi);
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int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write);
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int fast_off = tlb_mask_table_ofs(s, mem_index);
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unsigned s_mask = (1 << (opc & MO_SIZE)) - 1;
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TCGReg t_addr;
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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/* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4);
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tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off);
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/* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4);
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tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off);
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/* Extract the tlb index from the address into R0. */
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tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo,
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SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS));
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/* Extract the tlb index from the address into R0. */
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tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo,
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SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS));
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/*
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* Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
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* Load the tlb comparator into R2/R3 and the fast path addend into R1.
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*/
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QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
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if (cmp_off == 0) {
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if (s->addr_type == TCG_TYPE_I32) {
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tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
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/*
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* Add the tlb_table pointer, creating the CPUTLBEntry address in R1.
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* Load the tlb comparator into R2/R3 and the fast path addend into R1.
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*/
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QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
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if (cmp_off == 0) {
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if (s->addr_type == TCG_TYPE_I32) {
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tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2,
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TCG_REG_R1, TCG_REG_R0);
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} else {
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tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2,
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TCG_REG_R1, TCG_REG_R0);
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}
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} else {
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tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0);
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tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
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TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0);
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if (s->addr_type == TCG_TYPE_I32) {
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
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} else {
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tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
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}
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}
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} else {
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tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
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TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0);
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if (s->addr_type == TCG_TYPE_I32) {
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
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/* Load the tlb addend. */
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1,
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offsetof(CPUTLBEntry, addend));
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/*
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* Check alignment, check comparators.
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* Do this in 2-4 insns. Use MOVW for v7, if possible,
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* to reduce the number of sequential conditional instructions.
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* Almost all guests have at least 4k pages, which means that we need
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* to clear at least 9 bits even for an 8-byte memory, which means it
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* isn't worth checking for an immediate operand for BIC.
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*
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* For unaligned accesses, test the page of the last unit of alignment.
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* This leaves the least significant alignment bits unchanged, and of
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* course must be zero.
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*/
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t_addr = addrlo;
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if (a_mask < s_mask) {
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t_addr = TCG_REG_R0;
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tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr,
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addrlo, s_mask - a_mask);
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}
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if (use_armv7_instructions && s->page_bits <= 16) {
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tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask));
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tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
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t_addr, TCG_REG_TMP, 0);
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tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
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TCG_REG_R2, TCG_REG_TMP, 0);
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} else {
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tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off);
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if (a_mask) {
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tcg_debug_assert(a_mask <= 0xff);
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tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
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}
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tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr,
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SHIFT_IMM_LSR(s->page_bits));
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tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP,
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0, TCG_REG_R2, TCG_REG_TMP,
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SHIFT_IMM_LSL(s->page_bits));
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}
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}
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/* Load the tlb addend. */
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1,
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offsetof(CPUTLBEntry, addend));
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/*
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* Check alignment, check comparators.
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* Do this in 2-4 insns. Use MOVW for v7, if possible,
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* to reduce the number of sequential conditional instructions.
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* Almost all guests have at least 4k pages, which means that we need
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* to clear at least 9 bits even for an 8-byte memory, which means it
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* isn't worth checking for an immediate operand for BIC.
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*
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* For unaligned accesses, test the page of the last unit of alignment.
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* This leaves the least significant alignment bits unchanged, and of
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* course must be zero.
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*/
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t_addr = addrlo;
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if (a_mask < s_mask) {
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t_addr = TCG_REG_R0;
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tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr,
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addrlo, s_mask - a_mask);
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}
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if (use_armv7_instructions && s->page_bits <= 16) {
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tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask));
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tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP,
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t_addr, TCG_REG_TMP, 0);
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tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP, 0);
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} else {
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if (a_mask) {
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tcg_debug_assert(a_mask <= 0xff);
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tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
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if (s->addr_type != TCG_TYPE_I32) {
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tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0);
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}
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tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr,
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SHIFT_IMM_LSR(s->page_bits));
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tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP,
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0, TCG_REG_R2, TCG_REG_TMP,
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SHIFT_IMM_LSL(s->page_bits));
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}
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if (s->addr_type != TCG_TYPE_I32) {
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tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0);
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}
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#else
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if (a_mask) {
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} else if (a_mask) {
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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@ -1505,7 +1499,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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/* tst addr, #mask */
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tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask);
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}
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#endif
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return ldst;
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}
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@ -2931,12 +2924,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
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#ifndef CONFIG_SOFTMMU
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if (guest_base) {
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if (!tcg_use_softmmu && guest_base) {
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base);
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tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE);
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}
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#endif
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tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]);
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