target/i386: [tcg] Port to translate_insn
Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Emilio G. Cota <cota@braap.org> Message-Id: <150002195074.22386.16195894320027075398.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -4417,15 +4417,16 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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/* convert one instruction. s->base.is_jmp is set if the translation must
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be stopped. Return the next pc value */
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static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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target_ulong pc_start)
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static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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{
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CPUX86State *env = cpu->env_ptr;
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int b, prefixes;
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int shift;
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TCGMemOp ot, aflag, dflag;
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int modrm, reg, rm, mod, op, opreg, val;
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target_ulong next_eip, tval;
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int rex_w, rex_r;
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target_ulong pc_start = s->base.pc_next;
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s->pc_start = s->pc = pc_start;
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prefixes = 0;
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@ -8476,10 +8477,46 @@ static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
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}
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}
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static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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target_ulong pc_next = disas_insn(dc, cpu);
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if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) {
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/* if single step mode, we generate only one instruction and
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generate an exception */
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/* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
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the flag and abort the translation to give the irqs a
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chance to happen */
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gen_jmp_im(pc_next - dc->cs_base);
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gen_eob(dc);
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dc->base.is_jmp = DISAS_TOO_MANY;
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} else if ((dc->base.tb->cflags & CF_USE_ICOUNT)
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&& ((dc->base.pc_next & TARGET_PAGE_MASK)
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!= ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1)
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& TARGET_PAGE_MASK)
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|| (dc->base.pc_next & ~TARGET_PAGE_MASK) == 0)) {
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/* Do not cross the boundary of the pages in icount mode,
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it can cause an exception. Do it only when boundary is
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crossed by the first instruction in the block.
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If current instruction already crossed the bound - it's ok,
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because an exception hasn't stopped this code.
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*/
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gen_jmp_im(pc_next - dc->cs_base);
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gen_eob(dc);
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dc->base.is_jmp = DISAS_TOO_MANY;
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} else if ((pc_next - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32)) {
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gen_jmp_im(pc_next - dc->cs_base);
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gen_eob(dc);
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dc->base.is_jmp = DISAS_TOO_MANY;
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}
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dc->base.pc_next = pc_next;
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}
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/* generate intermediate code for basic block 'tb'. */
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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{
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CPUX86State *env = cs->env_ptr;
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DisasContext dc1, *dc = &dc1;
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int num_insns;
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int max_insns;
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@ -8525,39 +8562,20 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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gen_io_start();
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}
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dc->base.pc_next = disas_insn(env, dc, dc->base.pc_next);
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i386_tr_translate_insn(&dc->base, cs);
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/* stop translation if indicated */
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if (dc->base.is_jmp) {
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break;
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}
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/* if single step mode, we generate only one instruction and
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generate an exception */
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/* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
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the flag and abort the translation to give the irqs a
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change to be happen */
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if (dc->tf || dc->base.singlestep_enabled ||
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(dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) {
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gen_jmp_im(dc->base.pc_next - dc->cs_base);
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gen_eob(dc);
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break;
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}
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/* Do not cross the boundary of the pages in icount mode,
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it can cause an exception. Do it only when boundary is
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crossed by the first instruction in the block.
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If current instruction already crossed the bound - it's ok,
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because an exception hasn't stopped this code.
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*/
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if ((tb->cflags & CF_USE_ICOUNT)
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&& ((dc->base.pc_next & TARGET_PAGE_MASK)
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!= ((dc->base.pc_next + TARGET_MAX_INSN_SIZE - 1) & TARGET_PAGE_MASK)
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|| (dc->base.pc_next & ~TARGET_PAGE_MASK) == 0)) {
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if (dc->base.singlestep_enabled) {
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gen_jmp_im(dc->base.pc_next - dc->cs_base);
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gen_eob(dc);
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break;
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}
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/* if too long translation, stop generation too */
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if (tcg_op_buf_full() ||
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(dc->base.pc_next - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32) ||
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num_insns >= max_insns) {
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gen_jmp_im(dc->base.pc_next - dc->cs_base);
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gen_eob(dc);
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