target/arm: Move v8m_security_lookup to ptw.c
This function has one private helper, v8m_is_sau_exempt, so move that at the same time. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220604040607.269301-12-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
c8e436c9f7
commit
2c1f429df3
@ -9,7 +9,6 @@
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/log.h"
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#include "target/arm/idau.h"
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#include "trace.h"
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#include "cpu.h"
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#include "internals.h"
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@ -11693,128 +11692,6 @@ bool m_is_system_region(CPUARMState *env, uint32_t address)
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return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) == 0x7;
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}
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static bool v8m_is_sau_exempt(CPUARMState *env,
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uint32_t address, MMUAccessType access_type)
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{
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/* The architecture specifies that certain address ranges are
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* exempt from v8M SAU/IDAU checks.
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*/
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return
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(access_type == MMU_INST_FETCH && m_is_system_region(env, address)) ||
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(address >= 0xe0000000 && address <= 0xe0002fff) ||
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(address >= 0xe000e000 && address <= 0xe000efff) ||
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(address >= 0xe002e000 && address <= 0xe002efff) ||
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(address >= 0xe0040000 && address <= 0xe0041fff) ||
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(address >= 0xe00ff000 && address <= 0xe00fffff);
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}
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void v8m_security_lookup(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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V8M_SAttributes *sattrs)
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{
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/* Look up the security attributes for this address. Compare the
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* pseudocode SecurityCheck() function.
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* We assume the caller has zero-initialized *sattrs.
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*/
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ARMCPU *cpu = env_archcpu(env);
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int r;
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bool idau_exempt = false, idau_ns = true, idau_nsc = true;
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int idau_region = IREGION_NOTVALID;
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uint32_t addr_page_base = address & TARGET_PAGE_MASK;
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uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
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if (cpu->idau) {
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IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau);
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IDAUInterface *ii = IDAU_INTERFACE(cpu->idau);
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iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns,
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&idau_nsc);
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}
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if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) {
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/* 0xf0000000..0xffffffff is always S for insn fetches */
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return;
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}
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if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) {
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sattrs->ns = !regime_is_secure(env, mmu_idx);
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return;
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}
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if (idau_region != IREGION_NOTVALID) {
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sattrs->irvalid = true;
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sattrs->iregion = idau_region;
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}
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switch (env->sau.ctrl & 3) {
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case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
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break;
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case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
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sattrs->ns = true;
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break;
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default: /* SAU.ENABLE == 1 */
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for (r = 0; r < cpu->sau_sregion; r++) {
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if (env->sau.rlar[r] & 1) {
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uint32_t base = env->sau.rbar[r] & ~0x1f;
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uint32_t limit = env->sau.rlar[r] | 0x1f;
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if (base <= address && limit >= address) {
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if (base > addr_page_base || limit < addr_page_limit) {
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sattrs->subpage = true;
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}
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if (sattrs->srvalid) {
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/* If we hit in more than one region then we must report
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* as Secure, not NS-Callable, with no valid region
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* number info.
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*/
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sattrs->ns = false;
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sattrs->nsc = false;
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sattrs->sregion = 0;
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sattrs->srvalid = false;
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break;
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} else {
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if (env->sau.rlar[r] & 2) {
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sattrs->nsc = true;
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} else {
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sattrs->ns = true;
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}
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sattrs->srvalid = true;
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sattrs->sregion = r;
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}
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} else {
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/*
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* Address not in this region. We must check whether the
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* region covers addresses in the same page as our address.
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* In that case we must not report a size that covers the
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* whole page for a subsequent hit against a different MPU
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* region or the background region, because it would result
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* in incorrect TLB hits for subsequent accesses to
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* addresses that are in this MPU region.
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*/
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if (limit >= base &&
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ranges_overlap(base, limit - base + 1,
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addr_page_base,
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TARGET_PAGE_SIZE)) {
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sattrs->subpage = true;
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}
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}
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}
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}
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break;
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}
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/*
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* The IDAU will override the SAU lookup results if it specifies
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* higher security than the SAU does.
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*/
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if (!idau_ns) {
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if (sattrs->ns || (!idau_nsc && sattrs->nsc)) {
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sattrs->ns = false;
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sattrs->nsc = idau_nsc;
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}
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}
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}
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/* Combine either inner or outer cacheability attributes for normal
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* memory, according to table D4-42 and pseudocode procedure
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* CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
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126
target/arm/ptw.c
126
target/arm/ptw.c
@ -11,6 +11,7 @@
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#include "qemu/range.h"
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#include "cpu.h"
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#include "internals.h"
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#include "idau.h"
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#include "ptw.h"
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@ -766,6 +767,131 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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return !(*prot & (1 << access_type));
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}
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static bool v8m_is_sau_exempt(CPUARMState *env,
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uint32_t address, MMUAccessType access_type)
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{
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/*
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* The architecture specifies that certain address ranges are
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* exempt from v8M SAU/IDAU checks.
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*/
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return
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(access_type == MMU_INST_FETCH && m_is_system_region(env, address)) ||
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(address >= 0xe0000000 && address <= 0xe0002fff) ||
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(address >= 0xe000e000 && address <= 0xe000efff) ||
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(address >= 0xe002e000 && address <= 0xe002efff) ||
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(address >= 0xe0040000 && address <= 0xe0041fff) ||
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(address >= 0xe00ff000 && address <= 0xe00fffff);
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}
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void v8m_security_lookup(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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V8M_SAttributes *sattrs)
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{
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/*
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* Look up the security attributes for this address. Compare the
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* pseudocode SecurityCheck() function.
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* We assume the caller has zero-initialized *sattrs.
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*/
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ARMCPU *cpu = env_archcpu(env);
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int r;
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bool idau_exempt = false, idau_ns = true, idau_nsc = true;
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int idau_region = IREGION_NOTVALID;
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uint32_t addr_page_base = address & TARGET_PAGE_MASK;
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uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
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if (cpu->idau) {
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IDAUInterfaceClass *iic = IDAU_INTERFACE_GET_CLASS(cpu->idau);
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IDAUInterface *ii = IDAU_INTERFACE(cpu->idau);
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iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns,
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&idau_nsc);
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}
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if (access_type == MMU_INST_FETCH && extract32(address, 28, 4) == 0xf) {
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/* 0xf0000000..0xffffffff is always S for insn fetches */
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return;
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}
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if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) {
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sattrs->ns = !regime_is_secure(env, mmu_idx);
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return;
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}
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if (idau_region != IREGION_NOTVALID) {
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sattrs->irvalid = true;
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sattrs->iregion = idau_region;
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}
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switch (env->sau.ctrl & 3) {
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case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
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break;
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case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
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sattrs->ns = true;
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break;
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default: /* SAU.ENABLE == 1 */
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for (r = 0; r < cpu->sau_sregion; r++) {
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if (env->sau.rlar[r] & 1) {
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uint32_t base = env->sau.rbar[r] & ~0x1f;
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uint32_t limit = env->sau.rlar[r] | 0x1f;
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if (base <= address && limit >= address) {
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if (base > addr_page_base || limit < addr_page_limit) {
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sattrs->subpage = true;
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}
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if (sattrs->srvalid) {
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/*
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* If we hit in more than one region then we must report
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* as Secure, not NS-Callable, with no valid region
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* number info.
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*/
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sattrs->ns = false;
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sattrs->nsc = false;
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sattrs->sregion = 0;
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sattrs->srvalid = false;
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break;
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} else {
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if (env->sau.rlar[r] & 2) {
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sattrs->nsc = true;
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} else {
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sattrs->ns = true;
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}
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sattrs->srvalid = true;
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sattrs->sregion = r;
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}
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} else {
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/*
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* Address not in this region. We must check whether the
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* region covers addresses in the same page as our address.
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* In that case we must not report a size that covers the
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* whole page for a subsequent hit against a different MPU
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* region or the background region, because it would result
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* in incorrect TLB hits for subsequent accesses to
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* addresses that are in this MPU region.
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*/
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if (limit >= base &&
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ranges_overlap(base, limit - base + 1,
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addr_page_base,
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TARGET_PAGE_SIZE)) {
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sattrs->subpage = true;
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}
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}
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}
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}
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break;
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}
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/*
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* The IDAU will override the SAU lookup results if it specifies
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* higher security than the SAU does.
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*/
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if (!idau_ns) {
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if (sattrs->ns || (!idau_nsc && sattrs->nsc)) {
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sattrs->ns = false;
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sattrs->nsc = idau_nsc;
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}
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}
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}
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static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *txattrs,
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