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arm: Add dummy support for co-processor 15's secure config register

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Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Rob Herring 2012-01-13 17:25:08 +00:00 committed by Peter Maydell
parent d3cb6e2b06
commit 2be2762421
3 changed files with 13 additions and 1 deletions
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3
target-arm/cpu.h
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@ -116,6 +116,7 @@ typedef struct CPUARMState {
uint32_t c1_sys; /* System control register. */ uint32_t c1_sys; /* System control register. */
uint32_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_coproc; /* Coprocessor access register. */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
uint32_t c1_scr; /* secure config register. */
uint32_t c2_base0; /* MMU translation table base 0. */ uint32_t c2_base0; /* MMU translation table base 0. */
uint32_t c2_base1; /* MMU translation table base 1. */ uint32_t c2_base1; /* MMU translation table base 1. */
uint32_t c2_control; /* MMU translation table base control. */ uint32_t c2_control; /* MMU translation table base control. */
@ -452,7 +453,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define cpu_signal_handler cpu_arm_signal_handler #define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list #define cpu_list arm_cpu_list
#define CPU_SAVE_VERSION 5 #define CPU_SAVE_VERSION 6
/* MMU modes definitions */ /* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel #define MMU_MODE0_SUFFIX _kernel

9
target-arm/helper.c
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@ -1440,6 +1440,11 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
} }
goto bad_reg; goto bad_reg;
case 1: /* System configuration. */ case 1: /* System configuration. */
if (arm_feature(env, ARM_FEATURE_V7)
&& op1 == 0 && crm == 1 && op2 == 0) {
env->cp15.c1_scr = val;
break;
}
if (arm_feature(env, ARM_FEATURE_OMAPCP)) if (arm_feature(env, ARM_FEATURE_OMAPCP))
op2 = 0; op2 = 0;
switch (op2) { switch (op2) {
@ -1908,6 +1913,10 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
goto bad_reg; goto bad_reg;
} }
case 1: /* System configuration. */ case 1: /* System configuration. */
if (arm_feature(env, ARM_FEATURE_V7)
&& op1 == 0 && crm == 1 && op2 == 0) {
return env->cp15.c1_scr;
}
if (arm_feature(env, ARM_FEATURE_OMAPCP)) if (arm_feature(env, ARM_FEATURE_OMAPCP))
op2 = 0; op2 = 0;
switch (op2) { switch (op2) {

2
target-arm/machine.c
View File

@ -26,6 +26,7 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, env->cp15.c1_sys); qemu_put_be32(f, env->cp15.c1_sys);
qemu_put_be32(f, env->cp15.c1_coproc); qemu_put_be32(f, env->cp15.c1_coproc);
qemu_put_be32(f, env->cp15.c1_xscaleauxcr); qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
qemu_put_be32(f, env->cp15.c1_scr);
qemu_put_be32(f, env->cp15.c2_base0); qemu_put_be32(f, env->cp15.c2_base0);
qemu_put_be32(f, env->cp15.c2_base1); qemu_put_be32(f, env->cp15.c2_base1);
qemu_put_be32(f, env->cp15.c2_control); qemu_put_be32(f, env->cp15.c2_control);
@ -143,6 +144,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
env->cp15.c1_sys = qemu_get_be32(f); env->cp15.c1_sys = qemu_get_be32(f);
env->cp15.c1_coproc = qemu_get_be32(f); env->cp15.c1_coproc = qemu_get_be32(f);
env->cp15.c1_xscaleauxcr = qemu_get_be32(f); env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
env->cp15.c1_scr = qemu_get_be32(f);
env->cp15.c2_base0 = qemu_get_be32(f); env->cp15.c2_base0 = qemu_get_be32(f);
env->cp15.c2_base1 = qemu_get_be32(f); env->cp15.c2_base1 = qemu_get_be32(f);
env->cp15.c2_control = qemu_get_be32(f); env->cp15.c2_control = qemu_get_be32(f);