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target/arm: Implement fp16 for Neon VABS, VNEG of floats

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Rewrite Neon VABS/VNEG of floats to use gvec logical AND and XOR, so
that we can implement the fp16 version of the insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-26-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-08-28 19:33:34 +01:00
parent 4a15d9a3b3
commit 2b70d8cd09
1 changed files with 28 additions and 6 deletions
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34
target/arm/translate-neon.c.inc
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@ -3741,22 +3741,44 @@ static bool trans_VCNT(DisasContext *s, arg_2misc *a)
return do_2misc(s, a, gen_helper_neon_cnt_u8);
}
static void gen_VABS_F(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
uint32_t oprsz, uint32_t maxsz)
{
tcg_gen_gvec_andi(vece, rd_ofs, rm_ofs,
vece == MO_16 ? 0x7fff : 0x7fffffff,
oprsz, maxsz);
}
static bool trans_VABS_F(DisasContext *s, arg_2misc *a)
{
if (a->size != 2) {
if (a->size == MO_16) {
if (!dc_isar_feature(aa32_fp16_arith, s)) {
return false;
}
} else if (a->size != MO_32) {
return false;
}
/* TODO: FP16 : size == 1 */
return do_2misc(s, a, gen_helper_vfp_abss);
return do_2misc_vec(s, a, gen_VABS_F);
}
static void gen_VNEG_F(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
uint32_t oprsz, uint32_t maxsz)
{
tcg_gen_gvec_xori(vece, rd_ofs, rm_ofs,
vece == MO_16 ? 0x8000 : 0x80000000,
oprsz, maxsz);
}
static bool trans_VNEG_F(DisasContext *s, arg_2misc *a)
{
if (a->size != 2) {
if (a->size == MO_16) {
if (!dc_isar_feature(aa32_fp16_arith, s)) {
return false;
}
} else if (a->size != MO_32) {
return false;
}
/* TODO: FP16 : size == 1 */
return do_2misc(s, a, gen_helper_vfp_negs);
return do_2misc_vec(s, a, gen_VNEG_F);
}
static bool trans_VRECPE(DisasContext *s, arg_2misc *a)