cosmetics
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@173 c046a42c-6fe2-441c-8c8c-71466251a162
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3ebcc707d2
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33
exec-i386.c
33
exec-i386.c
@ -324,10 +324,8 @@ void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
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the effective address of the memory exception. 'is_write' is 1 if a
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write caused the exception and otherwise 0'. 'old_set' is the
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signal set which should be restored */
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static inline int handle_cpu_signal(unsigned long pc,
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unsigned long address,
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int is_write,
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sigset_t *old_set)
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static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
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int is_write, sigset_t *old_set)
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{
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#if defined(DEBUG_SIGNAL)
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printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n",
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@ -355,13 +353,13 @@ static inline int handle_cpu_signal(unsigned long pc,
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}
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}
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#if defined(__i386__)
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int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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{
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#if defined(__i386__)
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struct ucontext *uc = puc;
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unsigned long pc;
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sigset_t *pold_set;
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#ifndef REG_EIP
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/* for glibc 2.1 */
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@ -370,20 +368,23 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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#define REG_TRAPNO TRAPNO
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#endif
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pc = uc->uc_mcontext.gregs[REG_EIP];
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pold_set = &uc->uc_sigmask;
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return handle_cpu_signal(pc, (unsigned long)info->si_addr,
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uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
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(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
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pold_set);
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&uc->uc_sigmask);
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}
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#elif defined(__powerpc)
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int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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{
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struct ucontext *uc = puc;
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struct pt_regs *regs = uc->uc_mcontext.regs;
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unsigned long pc;
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sigset_t *pold_set;
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int is_write;
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pc = regs->nip;
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pold_set = &uc->uc_sigmask;
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is_write = 0;
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#if 0
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/* ppc 4xx case */
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@ -394,9 +395,11 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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is_write = 1;
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#endif
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return handle_cpu_signal(pc, (unsigned long)info->si_addr,
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is_write, pold_set);
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#else
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#error CPU specific signal handler needed
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return 0;
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#endif
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is_write, &uc->uc_sigmask);
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}
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#else
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#error CPU specific signal handler needed
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#endif
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