tcg/arm: Extract INSN_NOP
We'll want this for tcg_out_nop_fill. Signed-off-by: Richard Henderson <rth@twiddle.net>
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1507061637
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@ -160,8 +160,18 @@ typedef enum {
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INSN_DMB_ISH = 0x5bf07ff5,
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INSN_DMB_ISH = 0x5bf07ff5,
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INSN_DMB_MCR = 0xba0f07ee,
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INSN_DMB_MCR = 0xba0f07ee,
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/* Architected nop introduced in v6k. */
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/* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
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also Just So Happened to do nothing on pre-v6k so that we
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don't need to conditionalize it? */
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INSN_NOP_v6k = 0xe320f000,
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/* Otherwise the assembler uses mov r0,r0 */
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INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV,
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} ARMInsn;
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} ARMInsn;
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#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
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static const uint8_t tcg_cond_to_arm_cond[] = {
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static const uint8_t tcg_cond_to_arm_cond[] = {
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[TCG_COND_EQ] = COND_EQ,
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[TCG_COND_EQ] = COND_EQ,
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[TCG_COND_NE] = COND_NE,
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[TCG_COND_NE] = COND_NE,
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@ -375,16 +385,7 @@ static inline void tcg_out_dat_reg(TCGContext *s,
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static inline void tcg_out_nop(TCGContext *s)
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static inline void tcg_out_nop(TCGContext *s)
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{
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{
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if (use_armv7_instructions) {
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tcg_out32(s, INSN_NOP);
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/* Architected nop introduced in v6k. */
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/* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
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also Just So Happened to do nothing on pre-v6k so that we
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don't need to conditionalize it? */
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tcg_out32(s, 0xe320f000);
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} else {
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/* Prior to that the assembler uses mov r0, r0. */
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tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 0, 0, 0, SHIFT_IMM_LSL(0));
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}
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}
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}
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static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm)
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static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm)
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