hw/mpcore.c: Merge with hw/arm11mpcore.c
hw/mpcore.c is now implementing only ARM11MPCore specific peripherals, and is #included only from hw/arm11mpcore.c, so just merge it into that file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
parent
b12080cd50
commit
2a6ab1e368
130
hw/arm11mpcore.c
130
hw/arm11mpcore.c
@ -7,11 +7,139 @@
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* This code is licensed under the GPL.
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*/
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#include "sysbus.h"
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#include "qemu-timer.h"
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/* ??? The MPCore TRM says the on-chip controller has 224 external IRQ lines
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(+ 32 internal). However my test chip only exposes/reports 32.
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More importantly Linux falls over if more than 32 are present! */
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#define GIC_NIRQ 64
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#include "mpcore.c"
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#define NCPU 4
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static inline int
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gic_get_current_cpu(void)
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{
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return cpu_single_env->cpu_index;
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}
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#include "arm_gic.c"
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/* MPCore private memory region. */
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typedef struct mpcore_priv_state {
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gic_state gic;
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uint32_t scu_control;
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int iomemtype;
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uint32_t old_timer_status[8];
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uint32_t num_cpu;
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qemu_irq *timer_irq;
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MemoryRegion iomem;
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MemoryRegion container;
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DeviceState *mptimer;
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} mpcore_priv_state;
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/* Per-CPU private memory mapped IO. */
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static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
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unsigned size)
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{
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mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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int id;
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offset &= 0xff;
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/* SCU */
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switch (offset) {
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case 0x00: /* Control. */
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return s->scu_control;
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case 0x04: /* Configuration. */
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id = ((1 << s->num_cpu) - 1) << 4;
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return id | (s->num_cpu - 1);
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case 0x08: /* CPU status. */
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return 0;
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case 0x0c: /* Invalidate all. */
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return 0;
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default:
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hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
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}
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}
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static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,
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uint64_t value, unsigned size)
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{
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mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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offset &= 0xff;
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/* SCU */
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switch (offset) {
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case 0: /* Control register. */
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s->scu_control = value & 1;
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break;
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case 0x0c: /* Invalidate all. */
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/* This is a no-op as cache is not emulated. */
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break;
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default:
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hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
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}
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}
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static const MemoryRegionOps mpcore_scu_ops = {
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.read = mpcore_scu_read,
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.write = mpcore_scu_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void mpcore_timer_irq_handler(void *opaque, int irq, int level)
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{
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mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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if (level && !s->old_timer_status[irq]) {
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gic_set_pending_private(&s->gic, irq >> 1, 29 + (irq & 1));
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}
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s->old_timer_status[irq] = level;
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}
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static void mpcore_priv_map_setup(mpcore_priv_state *s)
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{
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int i;
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SysBusDevice *busdev = sysbus_from_qdev(s->mptimer);
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memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
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memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100);
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memory_region_add_subregion(&s->container, 0, &s->iomem);
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/* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
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* at 0x200, 0x300...
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*/
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for (i = 0; i < (s->num_cpu + 1); i++) {
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target_phys_addr_t offset = 0x100 + (i * 0x100);
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memory_region_add_subregion(&s->container, offset, &s->gic.cpuiomem[i]);
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}
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/* Add the regions for timer and watchdog for "current CPU" and
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* for each specific CPU.
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*/
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s->timer_irq = qemu_allocate_irqs(mpcore_timer_irq_handler,
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s, (s->num_cpu + 1) * 2);
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for (i = 0; i < (s->num_cpu + 1) * 2; i++) {
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/* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
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target_phys_addr_t offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
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memory_region_add_subregion(&s->container, offset,
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sysbus_mmio_get_region(busdev, i));
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}
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memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
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/* Wire up the interrupt from each watchdog and timer. */
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for (i = 0; i < s->num_cpu * 2; i++) {
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sysbus_connect_irq(busdev, i, s->timer_irq[i]);
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}
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}
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static int mpcore_priv_init(SysBusDevice *dev)
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{
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mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev);
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gic_init(&s->gic, s->num_cpu);
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s->mptimer = qdev_create(NULL, "arm_mptimer");
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qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
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qdev_init_nofail(s->mptimer);
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mpcore_priv_map_setup(s);
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sysbus_init_mmio(dev, &s->container);
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return 0;
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}
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/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
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controllers. The output of these, plus some of the raw input lines
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137
hw/mpcore.c
137
hw/mpcore.c
@ -1,137 +0,0 @@
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/*
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* ARM MPCore internal peripheral emulation (common code).
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "sysbus.h"
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#include "qemu-timer.h"
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#define NCPU 4
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static inline int
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gic_get_current_cpu(void)
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{
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return cpu_single_env->cpu_index;
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}
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#include "arm_gic.c"
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/* MPCore private memory region. */
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typedef struct mpcore_priv_state {
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gic_state gic;
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uint32_t scu_control;
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int iomemtype;
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uint32_t old_timer_status[8];
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uint32_t num_cpu;
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qemu_irq *timer_irq;
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MemoryRegion iomem;
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MemoryRegion container;
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DeviceState *mptimer;
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} mpcore_priv_state;
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/* Per-CPU private memory mapped IO. */
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static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
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unsigned size)
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{
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mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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int id;
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offset &= 0xff;
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/* SCU */
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switch (offset) {
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case 0x00: /* Control. */
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return s->scu_control;
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case 0x04: /* Configuration. */
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id = ((1 << s->num_cpu) - 1) << 4;
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return id | (s->num_cpu - 1);
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case 0x08: /* CPU status. */
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return 0;
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case 0x0c: /* Invalidate all. */
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return 0;
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default:
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hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
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}
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}
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static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,
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uint64_t value, unsigned size)
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{
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mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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offset &= 0xff;
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/* SCU */
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switch (offset) {
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case 0: /* Control register. */
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s->scu_control = value & 1;
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break;
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case 0x0c: /* Invalidate all. */
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/* This is a no-op as cache is not emulated. */
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break;
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default:
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hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
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}
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}
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static const MemoryRegionOps mpcore_scu_ops = {
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.read = mpcore_scu_read,
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.write = mpcore_scu_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void mpcore_timer_irq_handler(void *opaque, int irq, int level)
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{
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mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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if (level && !s->old_timer_status[irq]) {
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gic_set_pending_private(&s->gic, irq >> 1, 29 + (irq & 1));
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}
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s->old_timer_status[irq] = level;
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}
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static void mpcore_priv_map_setup(mpcore_priv_state *s)
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{
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int i;
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SysBusDevice *busdev = sysbus_from_qdev(s->mptimer);
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memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
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memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100);
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memory_region_add_subregion(&s->container, 0, &s->iomem);
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/* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
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* at 0x200, 0x300...
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*/
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for (i = 0; i < (s->num_cpu + 1); i++) {
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target_phys_addr_t offset = 0x100 + (i * 0x100);
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memory_region_add_subregion(&s->container, offset, &s->gic.cpuiomem[i]);
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}
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/* Add the regions for timer and watchdog for "current CPU" and
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* for each specific CPU.
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*/
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s->timer_irq = qemu_allocate_irqs(mpcore_timer_irq_handler,
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s, (s->num_cpu + 1) * 2);
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for (i = 0; i < (s->num_cpu + 1) * 2; i++) {
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/* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
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target_phys_addr_t offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
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memory_region_add_subregion(&s->container, offset,
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sysbus_mmio_get_region(busdev, i));
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}
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memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
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/* Wire up the interrupt from each watchdog and timer. */
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for (i = 0; i < s->num_cpu * 2; i++) {
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sysbus_connect_irq(busdev, i, s->timer_irq[i]);
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}
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}
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static int mpcore_priv_init(SysBusDevice *dev)
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{
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mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev);
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gic_init(&s->gic, s->num_cpu);
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s->mptimer = qdev_create(NULL, "arm_mptimer");
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qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
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qdev_init_nofail(s->mptimer);
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mpcore_priv_map_setup(s);
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sysbus_init_mmio(dev, &s->container);
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return 0;
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}
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