hw/armv7m_nvic: Use MemoryRegions for NVIC specific registers
Implement the NVIC specific register areas using a set of overlaid MemoryRegions in a container, rather than by having the arm_gic read/write functions use special purpose callbacks. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
parent
b3387ede2f
commit
2a29ddee82
33
hw/arm_gic.c
33
hw/arm_gic.c
@ -37,17 +37,17 @@ do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0)
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#endif
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#ifdef NVIC
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static const uint8_t gic_id[] =
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{ 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 };
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/* The NVIC has 16 internal vectors. However these are not exposed
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through the normal GIC interface. */
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#define GIC_BASE_IRQ 32
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#else
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static const uint8_t gic_id[] =
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{ 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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#define GIC_BASE_IRQ 0
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#endif
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static const uint8_t gic_id[] = {
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0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
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};
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#define FROM_SYSBUSGIC(type, dev) \
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DO_UPCAST(type, gic, FROM_SYSBUS(gic_state, dev))
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@ -312,7 +312,6 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
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cpu = gic_get_current_cpu(s);
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cm = 1 << cpu;
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if (offset < 0x100) {
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#ifndef NVIC
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if (offset == 0)
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return s->enabled;
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if (offset == 4)
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@ -323,7 +322,6 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
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/* Interrupt Security , RAZ/WI */
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return 0;
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}
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#endif
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goto bad_reg;
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} else if (offset < 0x200) {
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/* Interrupt Set/Clear Enable. */
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@ -385,6 +383,7 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
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} else {
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res = GIC_TARGET(irq);
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}
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#endif
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} else if (offset < 0xf00) {
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/* Interrupt Configuration. */
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irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ;
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@ -397,7 +396,6 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
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if (GIC_TEST_TRIGGER(irq + i))
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res |= (2 << (i * 2));
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}
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#endif
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} else if (offset < 0xfe0) {
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goto bad_reg;
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} else /* offset >= 0xfe0 */ {
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@ -424,13 +422,6 @@ static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
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static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
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{
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uint32_t val;
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#ifdef NVIC
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gic_state *s = (gic_state *)opaque;
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uint32_t addr;
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addr = offset;
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if (addr < 0x100 || addr > 0xd00)
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return nvic_readl(s, addr);
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#endif
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val = gic_dist_readw(opaque, offset);
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val |= gic_dist_readw(opaque, offset + 2) << 16;
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return val;
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@ -446,9 +437,6 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
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cpu = gic_get_current_cpu(s);
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if (offset < 0x100) {
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#ifdef NVIC
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goto bad_reg;
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#else
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if (offset == 0) {
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s->enabled = (value & 1);
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DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
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@ -459,7 +447,6 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
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} else {
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goto bad_reg;
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}
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#endif
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} else if (offset < 0x180) {
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/* Interrupt Set Enable. */
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irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
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@ -552,6 +539,7 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
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else if (irq < GIC_INTERNAL)
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value = ALL_CPU_MASK;
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s->irq_target[irq] = value & ALL_CPU_MASK;
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#endif
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} else if (offset < 0xf00) {
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/* Interrupt Configuration. */
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irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
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@ -571,7 +559,6 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
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GIC_CLEAR_TRIGGER(irq + i);
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}
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}
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#endif
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} else {
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/* 0xf00 is only handled for 32-bit writes. */
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goto bad_reg;
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@ -593,14 +580,6 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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gic_state *s = (gic_state *)opaque;
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#ifdef NVIC
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uint32_t addr;
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addr = offset;
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if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
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nvic_writel(s, addr, value);
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return;
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}
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#endif
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if (offset == 0xf00) {
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int cpu;
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int irq;
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@ -30,9 +30,16 @@ typedef struct {
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int64_t tick;
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QEMUTimer *timer;
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} systick;
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MemoryRegion sysregmem;
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MemoryRegion gic_iomem_alias;
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MemoryRegion container;
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uint32_t num_irq;
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} nvic_state;
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static const uint8_t nvic_id[] = {
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0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
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};
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/* qemu timers run at 1GHz. We want something closer to 1MHz. */
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#define SYSTICK_SCALE 1000ULL
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@ -358,12 +365,54 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
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case 0xd38: /* Bus Fault Address. */
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case 0xd3c: /* Aux Fault Status. */
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goto bad_reg;
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case 0xf00: /* Software Triggered Interrupt Register */
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if ((value & 0x1ff) < s->num_irq) {
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gic_set_pending_private(&s->gic, 0, value & 0x1ff);
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}
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break;
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default:
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bad_reg:
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hw_error("NVIC: Bad write offset 0x%x\n", offset);
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}
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}
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static uint64_t nvic_sysreg_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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/* At the moment we only support the ID registers for byte/word access.
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* This is not strictly correct as a few of the other registers also
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* allow byte access.
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*/
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uint32_t offset = addr;
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if (offset >= 0xfe0) {
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if (offset & 3) {
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return 0;
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}
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return nvic_id[(offset - 0xfe0) >> 2];
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}
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if (size == 4) {
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return nvic_readl(opaque, offset);
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}
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hw_error("NVIC: Bad read of size %d at offset 0x%x\n", size, offset);
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}
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static void nvic_sysreg_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned size)
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{
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uint32_t offset = addr;
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if (size == 4) {
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nvic_writel(opaque, offset, value);
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return;
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}
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hw_error("NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
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}
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static const MemoryRegionOps nvic_sysreg_ops = {
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.read = nvic_sysreg_read,
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.write = nvic_sysreg_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_nvic = {
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.name = "armv7m_nvic",
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.version_id = 1,
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@ -399,7 +448,30 @@ static int armv7m_nvic_init(SysBusDevice *dev)
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/* The NVIC always has only one CPU */
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s->gic.num_cpu = 1;
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gic_init(&s->gic, s->num_irq);
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memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->gic.iomem);
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/* The NVIC and system controller register area looks like this:
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* 0..0xff : system control registers, including systick
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* 0x100..0xcff : GIC-like registers
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* 0xd00..0xfff : system control registers
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* We use overlaying to put the GIC like registers
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* over the top of the system control register region.
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*/
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memory_region_init(&s->container, "nvic", 0x1000);
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/* The system register region goes at the bottom of the priority
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* stack as it covers the whole page.
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*/
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memory_region_init_io(&s->sysregmem, &nvic_sysreg_ops, s,
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"nvic_sysregs", 0x1000);
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memory_region_add_subregion(&s->container, 0, &s->sysregmem);
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/* Alias the GIC region so we can get only the section of it
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* we need, and layer it on top of the system register region.
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*/
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memory_region_init_alias(&s->gic_iomem_alias, "nvic-gic", &s->gic.iomem,
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0x100, 0xc00);
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memory_region_add_subregion_overlap(&s->container, 0x100, &s->gic.iomem, 1);
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/* Map the whole thing into system memory at the location required
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* by the v7M architecture.
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*/
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memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->container);
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s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);
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return 0;
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}
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