s390x/tcg: Factor out gen_addi_and_wrap_i64() from get_address()
Also properly wrap in 24bit mode. While at it, convert the comment (and drop the comment about fundamental TCG optimizations). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
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@ -382,32 +382,43 @@ static inline void gen_trap(DisasContext *s)
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gen_data_exception(0xff);
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}
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static void gen_addi_and_wrap_i64(DisasContext *s, TCGv_i64 dst, TCGv_i64 src,
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int64_t imm)
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{
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tcg_gen_addi_i64(dst, src, imm);
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if (!(s->base.tb->flags & FLAG_MASK_64)) {
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if (s->base.tb->flags & FLAG_MASK_32) {
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tcg_gen_andi_i64(dst, dst, 0x7fffffff);
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} else {
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tcg_gen_andi_i64(dst, dst, 0x00ffffff);
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}
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}
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}
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static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
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{
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TCGv_i64 tmp = tcg_temp_new_i64();
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bool need_31 = !(s->base.tb->flags & FLAG_MASK_64);
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/* Note that d2 is limited to 20 bits, signed. If we crop negative
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displacements early we create larger immedate addends. */
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/* Note that addi optimizes the imm==0 case. */
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/*
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* Note that d2 is limited to 20 bits, signed. If we crop negative
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* displacements early we create larger immedate addends.
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*/
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if (b2 && x2) {
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tcg_gen_add_i64(tmp, regs[b2], regs[x2]);
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tcg_gen_addi_i64(tmp, tmp, d2);
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gen_addi_and_wrap_i64(s, tmp, tmp, d2);
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} else if (b2) {
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tcg_gen_addi_i64(tmp, regs[b2], d2);
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gen_addi_and_wrap_i64(s, tmp, regs[b2], d2);
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} else if (x2) {
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tcg_gen_addi_i64(tmp, regs[x2], d2);
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} else {
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if (need_31) {
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d2 &= 0x7fffffff;
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need_31 = false;
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gen_addi_and_wrap_i64(s, tmp, regs[x2], d2);
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} else if (!(s->base.tb->flags & FLAG_MASK_64)) {
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if (s->base.tb->flags & FLAG_MASK_32) {
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tcg_gen_movi_i64(tmp, d2 & 0x7fffffff);
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} else {
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tcg_gen_movi_i64(tmp, d2 & 0x00ffffff);
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}
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} else {
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tcg_gen_movi_i64(tmp, d2);
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}
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if (need_31) {
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tcg_gen_andi_i64(tmp, tmp, 0x7fffffff);
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}
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return tmp;
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}
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