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target-arm queue:

Browse Source 
* hw/arm/virt: Add properties to allow more granular
    configuration of use of highmem space
  * target/arm: Add Cortex-A55 CPU
  * hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
  * Implement FEAT_EVT
  * Some 3-phase-reset conversions for Arm GIC, SMMU
  * hw/arm/boot: set initrd with #address-cells type in fdt
  * hw/misc: Move some arm-related files from specific_ss into softmmu_ss
  * Restrict arm_cpu_exec_interrupt() to TCG accelerator
 -----BEGIN PGP SIGNATURE-----
 
 iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmObW5wZHHBldGVyLm1h
 eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3nWUD/4xKR9eAX9NTgASnvW3MffZ
 GMkCW8TVFJdJy7rNq7TvPfdBEieVwrAGUmsTpkqN41/CHIIwIfssLzq6k1iliCOa
 /BrqA6p/vff+gRfV0rEgy7i/VsHmWzD5TU6qR/Jm899HA1ZsHGUFHzjs5p+V9Uzz
 r3awYTYsYbmuUgeoCaAQhbsyLCRmSi7gVbxeEc6UZst36xZEVwG8tPTwnhZUk55E
 KkZkSPvGiQ+1VKeGnL2yvjGS8blZnJL55oJ7wI7yAypCxy6gudB1HGegaNPnNcxf
 9lwph5sYaXbc0vyyAK3EJ+KUaJV9ZDU/ipjt3o88egYSYlB40IRVH1d+3ckZKSdG
 EBlD2vIx4vHjaIUXorB9U6BuktBsPtDmJ6jEsTT+cbb8roGDMB/opDZMNQB4WMIU
 kVEGZg7o3qkNDruAQOjakz8kOLq1J/ZKXBkLKWAsTTzdfMlnOMxAbFuFMxut7a+q
 JULMPjX9dBJDhsjE841QkAbYst1phDg8hCc00JB6Rbrl39jr4GZWfvaLKnci17ts
 nskPa/ElXvQj5WLhNZmn6vAco8mtGeDHzSNPnAoCCcDHd+hwfXkXKkweWZzzAr3f
 /PprDZy4hrksYqyYa9YMMQjHOlXQrJs5GntptnZwQQR2hhuQcCnBSNKxF+G6tk+K
 7Q1FjpE2d8NvL8Ar+WaX8w==
 =YAjF
 -----END PGP SIGNATURE-----

Merge tag 'pull-target-arm-20221215-1' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/arm/virt: Add properties to allow more granular
   configuration of use of highmem space
 * target/arm: Add Cortex-A55 CPU
 * hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
 * Implement FEAT_EVT
 * Some 3-phase-reset conversions for Arm GIC, SMMU
 * hw/arm/boot: set initrd with #address-cells type in fdt
 * hw/misc: Move some arm-related files from specific_ss into softmmu_ss
 * Restrict arm_cpu_exec_interrupt() to TCG accelerator

# gpg: Signature made Thu 15 Dec 2022 17:38:36 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20221215-1' of https://git.linaro.org/people/pmaydell/qemu-arm: (28 commits)
  target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator
  hw/misc: Move some arm-related files from specific_ss into softmmu_ss
  hw/arm/boot: set initrd with #address-cells type in fdt
  hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset
  hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset
  hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset
  hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset
  hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset
  hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset
  hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset
  hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset
  hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset
  target/arm: Report FEAT_EVT for TCG '-cpu max'
  target/arm: Implement HCR_EL2.TID4 traps
  target/arm: Implement HCR_EL2.TICAB,TOCU traps
  target/arm: Implement HCR_EL2.TTLBOS traps
  target/arm: Implement HCR_EL2.TTLBIS traps
  target/arm: Allow relevant HCR bits to be written for FEAT_EVT
  hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
  target/arm: Add Cortex-A55 CPU
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2022-12-15 17:40:57 +00:00
commit 29dc49f031
26 changed files with 459 additions and 141 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
docs/system/arm/emulation.rst
View File

@ -26,6 +26,7 @@ the following architecture extensions:
- FEAT_DoubleFault (Double Fault Extension)
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
- FEAT_ETS (Enhanced Translation Synchronization)
- FEAT_EVT (Enhanced Virtualization Traps)
- FEAT_FCMA (Floating-point complex number instructions)
- FEAT_FHM (Floating-point half-precision multiplication instructions)
- FEAT_FP16 (Half-precision floating-point data processing)

18
docs/system/arm/virt.rst
View File

@ -54,6 +54,7 @@ Supported guest CPU types:
- ``cortex-a15`` (32-bit; the default)
- ``cortex-a35`` (64-bit)
- ``cortex-a53`` (64-bit)
- ``cortex-a55`` (64-bit)
- ``cortex-a57`` (64-bit)
- ``cortex-a72`` (64-bit)
- ``cortex-a76`` (64-bit)
@ -94,6 +95,23 @@ highmem
address space above 32 bits. The default is ``on`` for machine types
later than ``virt-2.12``.
compact-highmem
Set ``on``/``off`` to enable/disable the compact layout for high memory regions.
The default is ``on`` for machine types later than ``virt-7.2``.
highmem-redists
Set ``on``/``off`` to enable/disable the high memory region for GICv3 or
GICv4 redistributor. The default is ``on``. Setting this to ``off`` will
limit the maximum number of CPUs when GICv3 or GICv4 is used.
highmem-ecam
Set ``on``/``off`` to enable/disable the high memory region for PCI ECAM.
The default is ``on`` for machine types later than ``virt-3.0``.
highmem-mmio
Set ``on``/``off`` to enable/disable the high memory region for PCI MMIO.
The default is ``on``.
gic-version
Specify the version of the Generic Interrupt Controller (GIC) to provide.
Valid values are:

10
hw/arm/boot.c
View File

@ -656,15 +656,17 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
}
if (binfo->initrd_size) {
rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
binfo->initrd_start);
rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start",
acells, binfo->initrd_start);
if (rc < 0) {
fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
goto fail;
}
rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
binfo->initrd_start + binfo->initrd_size);
rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end",
acells,
binfo->initrd_start +
binfo->initrd_size);
if (rc < 0) {
fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
goto fail;

7
hw/arm/smmu-common.c
View File

@ -526,9 +526,9 @@ static void smmu_base_realize(DeviceState *dev, Error **errp)
}
}
static void smmu_base_reset(DeviceState *dev)
static void smmu_base_reset_hold(Object *obj)
{
SMMUState *s = ARM_SMMU(dev);
SMMUState *s = ARM_SMMU(obj);
g_hash_table_remove_all(s->configs);
g_hash_table_remove_all(s->iotlb);
@ -543,12 +543,13 @@ static Property smmu_dev_properties[] = {
static void smmu_base_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass);
device_class_set_props(dc, smmu_dev_properties);
device_class_set_parent_realize(dc, smmu_base_realize,
&sbc->parent_realize);
dc->reset = smmu_base_reset;
rc->phases.hold = smmu_base_reset_hold;
}
static const TypeInfo smmu_base_info = {

12
hw/arm/smmuv3.c
View File

@ -1431,12 +1431,14 @@ static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev)
}
}
static void smmu_reset(DeviceState *dev)
static void smmu_reset_hold(Object *obj)
{
SMMUv3State *s = ARM_SMMUV3(dev);
SMMUv3State *s = ARM_SMMUV3(obj);
SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
c->parent_reset(dev);
if (c->parent_phases.hold) {
c->parent_phases.hold(obj);
}
smmuv3_init_regs(s);
}
@ -1520,10 +1522,12 @@ static void smmuv3_instance_init(Object *obj)
static void smmuv3_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
SMMUv3Class *c = ARM_SMMUV3_CLASS(klass);
dc->vmsd = &vmstate_smmuv3;
device_class_set_parent_reset(dc, smmu_reset, &c->parent_reset);
resettable_class_set_parent_phases(rc, NULL, smmu_reset_hold, NULL,
&c->parent_phases);
c->parent_realize = dc->realize;
dc->realize = smmu_realize;
}

202
hw/arm/virt.c
View File

@ -174,6 +174,12 @@ static const MemMapEntry base_memmap[] = {
* Note the extended_memmap is sized so that it eventually also includes the
* base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
* index of base_memmap).
*
* The memory map for these Highmem IO Regions can be in legacy or compact
* layout, depending on 'compact-highmem' property. With legacy layout, the
* PA space for one specific region is always reserved, even if the region
* has been disabled or doesn't fit into the PA space. However, the PA space
* for the region won't be reserved in these circumstances with compact layout.
*/
static MemMapEntry extended_memmap[] = {
/* Additional 64 MB redist region (can contain up to 512 redistributors) */
@ -201,6 +207,7 @@ static const char *valid_cpus[] = {
ARM_CPU_TYPE_NAME("cortex-a15"),
ARM_CPU_TYPE_NAME("cortex-a35"),
ARM_CPU_TYPE_NAME("cortex-a53"),
ARM_CPU_TYPE_NAME("cortex-a55"),
ARM_CPU_TYPE_NAME("cortex-a57"),
ARM_CPU_TYPE_NAME("cortex-a72"),
ARM_CPU_TYPE_NAME("cortex-a76"),
@ -1608,9 +1615,11 @@ static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
static void virt_build_smbios(VirtMachineState *vms)
{
MachineClass *mc = MACHINE_GET_CLASS(vms);
MachineState *ms = MACHINE(vms);
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
uint8_t *smbios_tables, *smbios_anchor;
size_t smbios_tables_len, smbios_anchor_len;
struct smbios_phys_mem_area mem_array;
const char *product = "QEMU Virtual Machine";
if (kvm_enabled()) {
@ -1621,7 +1630,11 @@ static void virt_build_smbios(VirtMachineState *vms)
vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
true, SMBIOS_ENTRY_POINT_TYPE_64);
smbios_get_tables(MACHINE(vms), NULL, 0,
/* build the array of physical mem area from base_memmap */
mem_array.address = vms->memmap[VIRT_MEM].base;
mem_array.length = ms->ram_size;
smbios_get_tables(ms, &mem_array, 1,
&smbios_tables, &smbios_tables_len,
&smbios_anchor, &smbios_anchor_len,
&error_fatal);
@ -1690,6 +1703,58 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
return arm_cpu_mp_affinity(idx, clustersz);
}
static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
int index)
{
bool *enabled_array[] = {
&vms->highmem_redists,
&vms->highmem_ecam,
&vms->highmem_mmio,
};
assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
ARRAY_SIZE(enabled_array));
assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
return enabled_array[index - VIRT_LOWMEMMAP_LAST];
}
static void virt_set_high_memmap(VirtMachineState *vms,
hwaddr base, int pa_bits)
{
hwaddr region_base, region_size;
bool *region_enabled, fits;
int i;
for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
region_enabled = virt_get_high_memmap_enabled(vms, i);
region_base = ROUND_UP(base, extended_memmap[i].size);
region_size = extended_memmap[i].size;
vms->memmap[i].base = region_base;
vms->memmap[i].size = region_size;
/*
* Check each device to see if it fits in the PA space,
* moving highest_gpa as we go. For compatibility, move
* highest_gpa for disabled fitting devices as well, if
* the compact layout has been disabled.
*
* For each device that doesn't fit, disable it.
*/
fits = (region_base + region_size) <= BIT_ULL(pa_bits);
*region_enabled &= fits;
if (vms->highmem_compact && !*region_enabled) {
continue;
}
base = region_base + region_size;
if (fits) {
vms->highest_gpa = base - 1;
}
}
}
static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
{
MachineState *ms = MACHINE(vms);
@ -1745,39 +1810,7 @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
/* We know for sure that at least the memory fits in the PA space */
vms->highest_gpa = memtop - 1;
for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
hwaddr size = extended_memmap[i].size;
bool fits;
base = ROUND_UP(base, size);
vms->memmap[i].base = base;
vms->memmap[i].size = size;
/*
* Check each device to see if they fit in the PA space,
* moving highest_gpa as we go.
*
* For each device that doesn't fit, disable it.
*/
fits = (base + size) <= BIT_ULL(pa_bits);
if (fits) {
vms->highest_gpa = base + size - 1;
}
switch (i) {
case VIRT_HIGH_GIC_REDIST2:
vms->highmem_redists &= fits;
break;
case VIRT_HIGH_PCIE_ECAM:
vms->highmem_ecam &= fits;
break;
case VIRT_HIGH_PCIE_MMIO:
vms->highmem_mmio &= fits;
break;
}
base += size;
}
virt_set_high_memmap(vms, base, pa_bits);
if (device_memory_size > 0) {
ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
@ -2070,14 +2103,20 @@ static void machvirt_init(MachineState *machine)
if (vms->gic_version == VIRT_GIC_VERSION_2) {
virt_max_cpus = GIC_NCPU;
} else {
virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST) +
virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);
if (vms->highmem_redists) {
virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
}
}
if (max_cpus > virt_max_cpus) {
error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
"supported by machine 'mach-virt' (%d)",
max_cpus, virt_max_cpus);
if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
error_printf("Try 'highmem-redists=on' for more CPUs\n");
}
exit(1);
}
@ -2332,6 +2371,63 @@ static void virt_set_highmem(Object *obj, bool value, Error **errp)
vms->highmem = value;
}
static bool virt_get_compact_highmem(Object *obj, Error **errp)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
return vms->highmem_compact;
}
static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
vms->highmem_compact = value;
}
static bool virt_get_highmem_redists(Object *obj, Error **errp)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
return vms->highmem_redists;
}
static void virt_set_highmem_redists(Object *obj, bool value, Error **errp)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
vms->highmem_redists = value;
}
static bool virt_get_highmem_ecam(Object *obj, Error **errp)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
return vms->highmem_ecam;
}
static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
vms->highmem_ecam = value;
}
static bool virt_get_highmem_mmio(Object *obj, Error **errp)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
return vms->highmem_mmio;
}
static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
vms->highmem_mmio = value;
}
static bool virt_get_its(Object *obj, Error **errp)
{
VirtMachineState *vms = VIRT_MACHINE(obj);
@ -2946,6 +3042,35 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
"Set on/off to enable/disable using "
"physical address space above 32 bits");
object_class_property_add_bool(oc, "compact-highmem",
virt_get_compact_highmem,
virt_set_compact_highmem);
object_class_property_set_description(oc, "compact-highmem",
"Set on/off to enable/disable compact "
"layout for high memory regions");
object_class_property_add_bool(oc, "highmem-redists",
virt_get_highmem_redists,
virt_set_highmem_redists);
object_class_property_set_description(oc, "highmem-redists",
"Set on/off to enable/disable high "
"memory region for GICv3 or GICv4 "
"redistributor");
object_class_property_add_bool(oc, "highmem-ecam",
virt_get_highmem_ecam,
virt_set_highmem_ecam);
object_class_property_set_description(oc, "highmem-ecam",
"Set on/off to enable/disable high "
"memory region for PCI ECAM");
object_class_property_add_bool(oc, "highmem-mmio",
virt_get_highmem_mmio,
virt_set_highmem_mmio);
object_class_property_set_description(oc, "highmem-mmio",
"Set on/off to enable/disable high "
"memory region for PCI MMIO");
object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
virt_set_gic_version);
object_class_property_set_description(oc, "gic-version",
@ -3030,6 +3155,7 @@ static void virt_instance_init(Object *obj)
/* High memory is enabled by default */
vms->highmem = true;
vms->highmem_compact = !vmc->no_highmem_compact;
vms->gic_version = VIRT_GIC_VERSION_NOSEL;
vms->highmem_ecam = !vmc->no_highmem_ecam;
@ -3099,8 +3225,12 @@ DEFINE_VIRT_MACHINE_AS_LATEST(7, 2)
static void virt_machine_7_1_options(MachineClass *mc)
{
VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
virt_machine_7_2_options(mc);
compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
/* Compact layout for high memory regions was introduced with 7.2 */
vmc->no_highmem_compact = true;
}
DEFINE_VIRT_MACHINE(7, 1)

7
hw/intc/arm_gic_common.c
View File

@ -261,9 +261,9 @@ static inline void arm_gic_common_reset_irq_state(GICState *s, int first_cpu,
}
}
static void arm_gic_common_reset(DeviceState *dev)
static void arm_gic_common_reset_hold(Object *obj)
{
GICState *s = ARM_GIC_COMMON(dev);
GICState *s = ARM_GIC_COMMON(obj);
int i, j;
int resetprio;
@ -364,9 +364,10 @@ static Property arm_gic_common_properties[] = {
static void arm_gic_common_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
dc->reset = arm_gic_common_reset;
rc->phases.hold = arm_gic_common_reset_hold;
dc->realize = arm_gic_common_realize;
device_class_set_props(dc, arm_gic_common_properties);
dc->vmsd = &vmstate_gic;

14
hw/intc/arm_gic_kvm.c
View File

@ -38,7 +38,7 @@ DECLARE_OBJ_CHECKERS(GICState, KVMARMGICClass,
struct KVMARMGICClass {
ARMGICCommonClass parent_class;
DeviceRealize parent_realize;
void (*parent_reset)(DeviceState *dev);
ResettablePhases parent_phases;
};
void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level)
@ -473,12 +473,14 @@ static void kvm_arm_gic_get(GICState *s)
}
}
static void kvm_arm_gic_reset(DeviceState *dev)
static void kvm_arm_gic_reset_hold(Object *obj)
{
GICState *s = ARM_GIC_COMMON(dev);
GICState *s = ARM_GIC_COMMON(obj);
KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
kgc->parent_reset(dev);
if (kgc->parent_phases.hold) {
kgc->parent_phases.hold(obj);
}
if (kvm_arm_gic_can_save_restore(s)) {
kvm_arm_gic_put(s);
@ -593,6 +595,7 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);
@ -600,7 +603,8 @@ static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
agcc->post_load = kvm_arm_gic_put;
device_class_set_parent_realize(dc, kvm_arm_gic_realize,
&kgc->parent_realize);
device_class_set_parent_reset(dc, kvm_arm_gic_reset, &kgc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, kvm_arm_gic_reset_hold, NULL,
&kgc->parent_phases);
}
static const TypeInfo kvm_arm_gic_info = {

7
hw/intc/arm_gicv3_common.c
View File

@ -450,9 +450,9 @@ static void arm_gicv3_finalize(Object *obj)
g_free(s->redist_region_count);
}
static void arm_gicv3_common_reset(DeviceState *dev)
static void arm_gicv3_common_reset_hold(Object *obj)
{
GICv3State *s = ARM_GICV3_COMMON(dev);
GICv3State *s = ARM_GICV3_COMMON(obj);
int i;
for (i = 0; i < s->num_cpu; i++) {
@ -578,9 +578,10 @@ static Property arm_gicv3_common_properties[] = {
static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
dc->reset = arm_gicv3_common_reset;
rc->phases.hold = arm_gicv3_common_reset_hold;
dc->realize = arm_gicv3_common_realize;
device_class_set_props(dc, arm_gicv3_common_properties);
dc->vmsd = &vmstate_gicv3;

4
hw/intc/arm_gicv3_dist.c
View File

@ -390,9 +390,9 @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
* MBIS == 0 (message-based SPIs not supported)
* SecurityExtn == 1 if security extns supported
* CPUNumber == 0 since for us ARE is always 1
* ITLinesNumber == (num external irqs / 32) - 1
* ITLinesNumber == (((max SPI IntID + 1) / 32) - 1)
*/
int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1;
int itlinesnumber = (s->num_irq / 32) - 1;
/*
* SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and
* "security extensions not supported" always implies DS == 1,

14
hw/intc/arm_gicv3_its.c
View File

@ -27,7 +27,7 @@ DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
struct GICv3ITSClass {
GICv3ITSCommonClass parent_class;
void (*parent_reset)(DeviceState *dev);
ResettablePhases parent_phases;
};
/*
@ -1953,12 +1953,14 @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
}
}
static void gicv3_its_reset(DeviceState *dev)
static void gicv3_its_reset_hold(Object *obj)
{
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
c->parent_reset(dev);
if (c->parent_phases.hold) {
c->parent_phases.hold(obj);
}
/* Quiescent bit reset to 1 */
s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1);
@ -2012,12 +2014,14 @@ static Property gicv3_its_props[] = {
static void gicv3_its_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass);
GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
dc->realize = gicv3_arm_its_realize;
device_class_set_props(dc, gicv3_its_props);
device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset);
resettable_class_set_parent_phases(rc, NULL, gicv3_its_reset_hold, NULL,
&ic->parent_phases);
icc->post_load = gicv3_its_post_load;
}

7
hw/intc/arm_gicv3_its_common.c
View File

@ -122,9 +122,9 @@ void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
msi_nonbroken = true;
}
static void gicv3_its_common_reset(DeviceState *dev)
static void gicv3_its_common_reset_hold(Object *obj)
{
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
s->ctlr = 0;
s->cbaser = 0;
@ -137,8 +137,9 @@ static void gicv3_its_common_reset(DeviceState *dev)
static void gicv3_its_common_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
dc->reset = gicv3_its_common_reset;
rc->phases.hold = gicv3_its_common_reset_hold;
dc->vmsd = &vmstate_its;
}

14
hw/intc/arm_gicv3_its_kvm.c
View File

@ -37,7 +37,7 @@ DECLARE_OBJ_CHECKERS(GICv3ITSState, KVMARMITSClass,
struct KVMARMITSClass {
GICv3ITSCommonClass parent_class;
void (*parent_reset)(DeviceState *dev);
ResettablePhases parent_phases;
};
@ -197,13 +197,15 @@ static void kvm_arm_its_post_load(GICv3ITSState *s)
GITS_CTLR, &s->ctlr, true, &error_abort);
}
static void kvm_arm_its_reset(DeviceState *dev)
static void kvm_arm_its_reset_hold(Object *obj)
{
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s);
int i;
c->parent_reset(dev);
if (c->parent_phases.hold) {
c->parent_phases.hold(obj);
}
if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
KVM_DEV_ARM_ITS_CTRL_RESET)) {
@ -241,12 +243,14 @@ static Property kvm_arm_its_props[] = {
static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
KVMARMITSClass *ic = KVM_ARM_ITS_CLASS(klass);
dc->realize = kvm_arm_its_realize;
device_class_set_props(dc, kvm_arm_its_props);
device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset);
resettable_class_set_parent_phases(rc, NULL, kvm_arm_its_reset_hold, NULL,
&ic->parent_phases);
icc->send_msi = kvm_its_send_msi;
icc->pre_save = kvm_arm_its_pre_save;
icc->post_load = kvm_arm_its_post_load;

14
hw/intc/arm_gicv3_kvm.c
View File

@ -77,7 +77,7 @@ DECLARE_OBJ_CHECKERS(GICv3State, KVMARMGICv3Class,
struct KVMARMGICv3Class {
ARMGICv3CommonClass parent_class;
DeviceRealize parent_realize;
void (*parent_reset)(DeviceState *dev);
ResettablePhases parent_phases;
};
static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
@ -703,14 +703,16 @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
}
static void kvm_arm_gicv3_reset(DeviceState *dev)
static void kvm_arm_gicv3_reset_hold(Object *obj)
{
GICv3State *s = ARM_GICV3_COMMON(dev);
GICv3State *s = ARM_GICV3_COMMON(obj);
KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
DPRINTF("Reset\n");
kgc->parent_reset(dev);
if (kgc->parent_phases.hold) {
kgc->parent_phases.hold(obj);
}
if (s->migration_blocker) {
DPRINTF("Cannot put kernel gic state, no kernel interface\n");
@ -890,6 +892,7 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass);
@ -897,7 +900,8 @@ static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
agcc->post_load = kvm_arm_gicv3_put;
device_class_set_parent_realize(dc, kvm_arm_gicv3_realize,
&kgc->parent_realize);
device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset);
resettable_class_set_parent_phases(rc, NULL, kvm_arm_gicv3_reset_hold, NULL,
&kgc->parent_phases);
}
static const TypeInfo kvm_arm_gicv3_info = {

2
hw/misc/imx6_src.c
View File

@ -15,7 +15,7 @@
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "qemu/module.h"
#include "arm-powerctl.h"
#include "target/arm/arm-powerctl.h"
#include "hw/core/cpu.h"
#ifndef DEBUG_IMX6_SRC

1
hw/misc/iotkit-sysctl.c
View File

@ -30,7 +30,6 @@
#include "hw/qdev-properties.h"
#include "hw/arm/armsse-version.h"
#include "target/arm/arm-powerctl.h"
#include "target/arm/cpu.h"
REG32(SECDBGSTAT, 0x0)
REG32(SECDBGSET, 0x4)

11
hw/misc/meson.build
View File

@ -51,6 +51,7 @@ softmmu_ss.add(when: 'CONFIG_IMX', if_true: files(
'imx25_ccm.c',
'imx31_ccm.c',
'imx6_ccm.c',
'imx6_src.c',
'imx6ul_ccm.c',
'imx7_ccm.c',
'imx7_gpr.c',
@ -84,8 +85,8 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
))
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
'xlnx-versal-xramc.c',
@ -101,6 +102,7 @@ softmmu_ss.add(when: 'CONFIG_TZ_MPC', if_true: files('tz-mpc.c'))
softmmu_ss.add(when: 'CONFIG_TZ_MSC', if_true: files('tz-msc.c'))
softmmu_ss.add(when: 'CONFIG_TZ_PPC', if_true: files('tz-ppc.c'))
softmmu_ss.add(when: 'CONFIG_IOTKIT_SECCTL', if_true: files('iotkit-secctl.c'))
softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c'))
softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSINFO', if_true: files('iotkit-sysinfo.c'))
softmmu_ss.add(when: 'CONFIG_ARMSSE_CPU_PWRCTRL', if_true: files('armsse-cpu-pwrctrl.c'))
softmmu_ss.add(when: 'CONFIG_ARMSSE_CPUID', if_true: files('armsse-cpuid.c'))
@ -126,15 +128,12 @@ softmmu_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_ahb_apb_pnp.c'))
specific_ss.add(when: 'CONFIG_AVR_POWER', if_true: files('avr_power.c'))
specific_ss.add(when: 'CONFIG_IMX', if_true: files('imx6_src.c'))
specific_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c'))
specific_ss.add(when: 'CONFIG_MAC_VIA', if_true: files('mac_via.c'))
specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_cmgcr.c', 'mips_cpc.c'))
specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c'))
specific_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
softmmu_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
# HPPA devices
softmmu_ss.add(when: 'CONFIG_LASI', if_true: files('lasi.c'))

2
include/hw/arm/smmuv3.h
View File

@ -77,7 +77,7 @@ struct SMMUv3Class {
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
ResettablePhases parent_phases;
};
#define TYPE_ARM_SMMUV3 "arm-smmuv3"

2
include/hw/arm/virt.h
View File

@ -125,6 +125,7 @@ struct VirtMachineClass {
bool no_pmu;
bool claim_edge_triggered_timers;
bool smbios_old_sys_ver;
bool no_highmem_compact;
bool no_highmem_ecam;
bool no_ged; /* Machines < 4.2 have no support for ACPI GED device */
bool kvm_no_adjvtime;
@ -144,6 +145,7 @@ struct VirtMachineState {
PFlashCFI01 *flash[2];
bool secure;
bool highmem;
bool highmem_compact;
bool highmem_ecam;
bool highmem_mmio;
bool highmem_redists;

2
include/hw/misc/xlnx-zynqmp-apu-ctrl.h
View File

@ -13,7 +13,7 @@
#include "hw/sysbus.h"
#include "hw/register.h"
#include "target/arm/cpu.h"
#include "target/arm/cpu-qom.h"
#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL)

5
target/arm/cpu.c
View File

@ -528,7 +528,7 @@ static void arm_cpu_reset(DeviceState *dev)
arm_rebuild_hflags(env);
}
#ifndef CONFIG_USER_ONLY
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
unsigned int target_el,
@ -725,7 +725,8 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
cc->tcg_ops->do_interrupt(cs);
return true;
}
#endif /* !CONFIG_USER_ONLY */
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
void arm_cpu_update_virq(ARMCPU *cpu)
{

30
target/arm/cpu.h
View File

@ -3757,6 +3757,16 @@ static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
}
static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id)
{
return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1;
}
static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
{
return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2;
}
static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
{
return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
@ -4029,6 +4039,16 @@ static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
}
static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
}
static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
}
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
@ -4313,6 +4333,16 @@ static inline bool isar_feature_any_ras(const ARMISARegisters *id)
return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
}
static inline bool isar_feature_any_half_evt(const ARMISARegisters *id)
{
return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id);
}
static inline bool isar_feature_any_evt(const ARMISARegisters *id)
{
return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id);
}
/*
* Forward to the above feature tests given an ARMCPU pointer.
*/

70
target/arm/cpu64.c
View File

@ -792,6 +792,74 @@ static void aarch64_a53_initfn(Object *obj)
define_cortex_a72_a57_a53_cp_reginfo(cpu);
}
static void aarch64_a55_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
cpu->dtb_compatible = "arm,cortex-a55";
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
set_feature(&cpu->env, ARM_FEATURE_EL2);
set_feature(&cpu->env, ARM_FEATURE_EL3);
set_feature(&cpu->env, ARM_FEATURE_PMU);
/* Ordered by B2.4 AArch64 registers by functional group */
cpu->clidr = 0x82000023;
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
cpu->dcz_blocksize = 4; /* 64 bytes */
cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x04010088;
cpu->isar.id_isar0 = 0x02101110;
cpu->isar.id_isar1 = 0x13112111;
cpu->isar.id_isar2 = 0x21232042;
cpu->isar.id_isar3 = 0x01112131;
cpu->isar.id_isar4 = 0x00011142;
cpu->isar.id_isar5 = 0x01011121;
cpu->isar.id_isar6 = 0x00000010;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211;
cpu->isar.id_mmfr4 = 0x00021110;
cpu->isar.id_pfr0 = 0x10010131;
cpu->isar.id_pfr1 = 0x00011011;
cpu->isar.id_pfr2 = 0x00000011;
cpu->midr = 0x412FD050; /* r2p0 */
cpu->revidr = 0;
/* From B2.23 CCSIDR_EL1 */
cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
/* From B2.96 SCTLR_EL3 */
cpu->reset_sctlr = 0x30c50838;
/* From B4.45 ICH_VTR_EL2 */
cpu->gic_num_lrs = 4;
cpu->gic_vpribits = 5;
cpu->gic_vprebits = 5;
cpu->gic_pribits = 5;
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043;
/* From D5.4 AArch64 PMU register summary */
cpu->isar.reset_pmcr_el0 = 0x410b3000;
}
static void aarch64_a72_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@ -1186,6 +1254,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */
t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
cpu->isar.id_aa64mmfr2 = t;
@ -1243,6 +1312,7 @@ static const ARMCPUInfo aarch64_cpus[] = {
{ .name = "cortex-a35", .initfn = aarch64_a35_initfn },
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
{ .name = "cortex-a55", .initfn = aarch64_a55_initfn },
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
{ .name = "cortex-a76", .initfn = aarch64_a76_initfn },
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },

1
target/arm/cpu_tcg.c
View File

@ -65,6 +65,7 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
cpu->isar.id_mmfr4 = t;
t = cpu->isar.id_mmfr5;

135
target/arm/helper.c
View File

@ -362,6 +362,30 @@ static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
if (arm_current_el(env) == 1 &&
(arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) {
return CP_ACCESS_TRAP_EL2;
}
return CP_ACCESS_OK;
}
#ifdef TARGET_AARCH64
/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
if (arm_current_el(env) == 1 &&
(arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) {
return CP_ACCESS_TRAP_EL2;
}
return CP_ACCESS_OK;
}
#endif
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
ARMCPU *cpu = env_archcpu(env);
@ -1871,11 +1895,12 @@ static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
scr_write(env, ri, 0);
}
static CPAccessResult access_aa64_tid2(CPUARMState *env,
const ARMCPRegInfo *ri,
bool isread)
static CPAccessResult access_tid4(CPUARMState *env,
const ARMCPRegInfo *ri,
bool isread)
{
if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) {
if (arm_current_el(env) == 1 &&
(arm_hcr_el2_eff(env) & (HCR_TID2 | HCR_TID4))) {
return CP_ACCESS_TRAP_EL2;
}
@ -2106,12 +2131,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_R,
.accessfn = access_aa64_tid2,
.accessfn = access_tid4,
.readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
{ .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
.access = PL1_RW,
.accessfn = access_aa64_tid2,
.accessfn = access_tid4,
.writefn = csselr_write, .resetvalue = 0,
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
offsetof(CPUARMState, cp15.csselr_ns) } },
@ -2206,16 +2231,16 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
static const ARMCPRegInfo v7mp_cp_reginfo[] = {
/* 32 bit TLB invalidates, Inner Shareable */
{ .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.writefn = tlbiall_is_write },
{ .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.writefn = tlbimva_is_write },
{ .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.writefn = tlbiasid_is_write },
{ .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.writefn = tlbimvaa_is_write },
};
@ -4249,9 +4274,7 @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
return CP_ACCESS_OK;
}
static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
const ARMCPRegInfo *ri,
bool isread)
static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcrflags)
{
/* Cache invalidate/clean to Point of Unification... */
switch (arm_current_el(env)) {
@ -4262,8 +4285,8 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
}
/* fall through */
case 1:
/* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
if (arm_hcr_el2_eff(env) & HCR_TPU) {
/* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
if (arm_hcr_el2_eff(env) & hcrflags) {
return CP_ACCESS_TRAP_EL2;
}
break;
@ -4271,6 +4294,18 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
return CP_ACCESS_OK;
}
static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
return do_cacheop_pou_access(env, HCR_TICAB | HCR_TPU);
}
static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU);
}
/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
* Page D4-1736 (DDI0487A.b)
*/
@ -4911,15 +4946,15 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NOP,
.accessfn = aa64_cacheop_pou_access },
.accessfn = access_ticab },
{ .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
.access = PL1_W, .type = ARM_CP_NOP,
.accessfn = aa64_cacheop_pou_access },
.accessfn = access_tocu },
{ .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
.access = PL0_W, .type = ARM_CP_NOP,
.accessfn = aa64_cacheop_pou_access },
.accessfn = access_tocu },
{ .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
.access = PL1_W, .accessfn = aa64_cacheop_poc_access,
@ -4937,7 +4972,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
.access = PL0_W, .type = ARM_CP_NOP,
.accessfn = aa64_cacheop_pou_access },
.accessfn = access_tocu },
{ .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
.access = PL0_W, .type = ARM_CP_NOP,
@ -4948,27 +4983,27 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
/* TLBI operations */
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vmalle1is_write },
{ .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vmalle1is_write },
{ .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
@ -5078,10 +5113,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
#endif
/* TLB invalidate last level of translation table walk */
{ .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.writefn = tlbimva_is_write },
{ .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
.writefn = tlbimvaa_is_write },
{ .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
@ -5114,13 +5149,13 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.writefn = tlbiipas2is_hyp_write },
/* 32 bit cache operations */
{ .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_ticab },
{ .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
.type = ARM_CP_NOP, .access = PL1_W },
{ .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
{ .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
{ .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
.type = ARM_CP_NOP, .access = PL1_W },
{ .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
@ -5134,7 +5169,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
{ .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
{ .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
{ .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
@ -5267,6 +5302,12 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
}
}
if (cpu_isar_feature(any_evt, cpu)) {
valid_mask |= HCR_TTLBIS | HCR_TTLBOS | HCR_TICAB | HCR_TOCU | HCR_TID4;
} else if (cpu_isar_feature(any_half_evt, cpu)) {
valid_mask |= HCR_TICAB | HCR_TOCU | HCR_TID4;
}
/* Clear RES0 bits. */
value &= valid_mask;
@ -6720,35 +6761,35 @@ static const ARMCPRegInfo pauth_reginfo[] = {
static const ARMCPRegInfo tlbirange_reginfo[] = {
{ .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_rvae1is_write },
{ .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
@ -6835,27 +6876,27 @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
static const ARMCPRegInfo tlbios_reginfo[] = {
{ .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vmalle1is_write },
{ .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vmalle1is_write },
{ .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
.access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
.access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae1is_write },
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
@ -7241,7 +7282,7 @@ static const ARMCPRegInfo ccsidr2_reginfo[] = {
{ .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2,
.access = PL1_R,
.accessfn = access_aa64_tid2,
.accessfn = access_tid4,
.readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
};
@ -7541,7 +7582,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.name = "CLIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid2,
.accessfn = access_tid4,
.resetvalue = cpu->clidr
};
define_one_arm_cp_reg(cpu, &clidr);

8
target/arm/kvm-consts.h
View File

@ -14,16 +14,16 @@
#ifndef ARM_KVM_CONSTS_H
#define ARM_KVM_CONSTS_H
#ifdef NEED_CPU_H
#ifdef CONFIG_KVM
#include <linux/kvm.h>
#include <linux/psci.h>
#define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y)
#endif
#endif
#else
#ifndef MISMATCH_CHECK
#define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0)
#endif
#define CP_REG_SIZE_SHIFT 52