target/sparc: Implement STDFQ
Invalid encoding of addr should raise TT_ILL_INSN, so check before supervisor, which might raise TT_PRIV_INSN. Clear QNE after execution. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2340 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Tested-by: Carl Hauser <chauser@pullman.com>
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@ -645,7 +645,7 @@ STFSR 11 00000 100101 ..... . ............. @n_r_ri
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STXFSR 11 00001 100101 ..... . ............. @n_r_ri
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{
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STQF 11 ..... 100110 ..... . ............. @q_r_ri_na # v9
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STDFQ 11 ----- 100110 ----- - -------------
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STDFQ 11 ..... 100110 ..... . ............. @r_r_ri # v7,v8
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}
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STDF 11 ..... 100111 ..... . ............. @d_r_ri_na
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@ -4531,19 +4531,43 @@ TRANS(STQFA, 64, do_st_fpr, a, MO_128)
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static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a)
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{
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TCGv addr;
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if (!avail_32(dc)) {
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return false;
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}
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addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
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if (addr == NULL) {
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return false;
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}
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if (!supervisor(dc)) {
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return raise_priv(dc);
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}
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#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
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if (gen_trap_ifnofpu(dc)) {
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return true;
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}
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if (!dc->fsr_qne) {
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gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
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return true;
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}
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/* Store the single element from the queue. */
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TCGv_i64 fq = tcg_temp_new_i64();
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tcg_gen_ld_i64(fq, tcg_env, offsetof(CPUSPARCState, fq.d));
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tcg_gen_qemu_st_i64(fq, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN_4);
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/* Mark the queue empty, transitioning to fp_execute state. */
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tcg_gen_st_i32(tcg_constant_i32(0), tcg_env,
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offsetof(CPUSPARCState, fsr_qne));
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dc->fsr_qne = 0;
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return advance_pc(dc);
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#else
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qemu_build_not_reached();
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#endif
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}
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static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a)
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{
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TCGv addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
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