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target/sparc: Implement STDFQ

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Invalid encoding of addr should raise TT_ILL_INSN, so
check before supervisor, which might raise TT_PRIV_INSN.
Clear QNE after execution.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2340
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Carl Hauser <chauser@pullman.com>
This commit is contained in:
Richard Henderson 2024-08-16 14:12:59 +10:00
parent 5a165e2615
commit 29b99802aa
2 changed files with 27 additions and 3 deletions
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2
target/sparc/insns.decode
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@ -645,7 +645,7 @@ STFSR 11 00000 100101 ..... . ............. @n_r_ri
STXFSR 11 00001 100101 ..... . ............. @n_r_ri STXFSR 11 00001 100101 ..... . ............. @n_r_ri
{ {
STQF 11 ..... 100110 ..... . ............. @q_r_ri_na # v9 STQF 11 ..... 100110 ..... . ............. @q_r_ri_na # v9
STDFQ 11 ----- 100110 ----- - ------------- STDFQ 11 ..... 100110 ..... . ............. @r_r_ri # v7,v8
} }
STDF 11 ..... 100111 ..... . ............. @d_r_ri_na STDF 11 ..... 100111 ..... . ............. @d_r_ri_na

28
target/sparc/translate.c
View File

@ -4531,17 +4531,41 @@ TRANS(STQFA, 64, do_st_fpr, a, MO_128)
static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a) static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a)
{ {
TCGv addr;
if (!avail_32(dc)) { if (!avail_32(dc)) {
return false; return false;
} }
addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
if (addr == NULL) {
return false;
}
if (!supervisor(dc)) { if (!supervisor(dc)) {
return raise_priv(dc); return raise_priv(dc);
} }
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
if (gen_trap_ifnofpu(dc)) { if (gen_trap_ifnofpu(dc)) {
return true; return true;
} }
gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); if (!dc->fsr_qne) {
return true; gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR);
return true;
}
/* Store the single element from the queue. */
TCGv_i64 fq = tcg_temp_new_i64();
tcg_gen_ld_i64(fq, tcg_env, offsetof(CPUSPARCState, fq.d));
tcg_gen_qemu_st_i64(fq, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN_4);
/* Mark the queue empty, transitioning to fp_execute state. */
tcg_gen_st_i32(tcg_constant_i32(0), tcg_env,
offsetof(CPUSPARCState, fsr_qne));
dc->fsr_qne = 0;
return advance_pc(dc);
#else
qemu_build_not_reached();
#endif
} }
static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a) static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a)