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target/i386: do not include undefined bits in the AMD topoext leaf

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Commit d7c72735f6 ("target/i386: Add new EPYC CPU versions with updated
cache_info", 2023-05-08) ensured that AMD-defined CPU models did not
have the 'complex_indexing' bit set, but left it set in "-cpu host"
which uses the default ("legacy") cache information.

Reimplement that commit using a CPU feature, so that it can be applied
to all guests using a new machine type, independent of the CPU model.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2024-07-03 11:29:17 +02:00
parent 9b40d376f6
commit 29a51b2bb5
3 changed files with 8 additions and 0 deletions
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1
hw/i386/pc.c
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@ -80,6 +80,7 @@
{ "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
GlobalProperty pc_compat_9_0[] = {
{ TYPE_X86_CPU, "x-amd-topoext-features-only", "false" },
{ TYPE_X86_CPU, "x-l1-cache-per-thread", "false" },
{ TYPE_X86_CPU, "guest-phys-bits", "0" },
{ "sev-guest", "legacy-vm-type", "true" },

4
target/i386/cpu.c
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@ -6982,6 +6982,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*eax = *ebx = *ecx = *edx = 0;
break;
}
if (cpu->amd_topoext_features_only) {
*edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE;
}
break;
case 0x8000001E:
if (cpu->core_id <= 255) {
@ -8293,6 +8296,7 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true),
DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true),
DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid,

3
target/i386/cpu.h
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@ -2104,6 +2104,9 @@ struct ArchCPU {
/* Only advertise CPUID leaves defined by the vendor */
bool vendor_cpuid_only;
/* Only advertise TOPOEXT features that AMD defines */
bool amd_topoext_features_only;
/* Enable auto level-increase for Intel Processor Trace leave */
bool intel_pt_auto_level;