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target-mips: cleanup load/store operations

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Load/store operations use macros for historical reasons. Now that there
is no point in keeping them, replace them by direct calls to qemu_ld/st.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2012-10-09 21:53:20 +02:00
parent 5f7319cd84
commit 2910c6cbaa
1 changed files with 35 additions and 64 deletions
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99
target-mips/translate.c
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@ -1484,35 +1484,6 @@ FOP_CONDS(abs, 1, ps, FMT_PS, 64)
#undef gen_ldcmp_fpr64 #undef gen_ldcmp_fpr64
/* load/store instructions. */ /* load/store instructions. */
#define OP_LD(insn,fname) \
static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
{ \
tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
}
OP_LD(lb,ld8s);
OP_LD(lbu,ld8u);
OP_LD(lh,ld16s);
OP_LD(lhu,ld16u);
OP_LD(lw,ld32s);
#if defined(TARGET_MIPS64)
OP_LD(lwu,ld32u);
OP_LD(ld,ld64);
#endif
#undef OP_LD
#define OP_ST(insn,fname) \
static inline void op_st_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
{ \
tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
}
OP_ST(sb,st8);
OP_ST(sh,st16);
OP_ST(sw,st32);
#if defined(TARGET_MIPS64)
OP_ST(sd,st64);
#endif
#undef OP_ST
#ifdef CONFIG_USER_ONLY #ifdef CONFIG_USER_ONLY
#define OP_LD_ATOMIC(insn,fname) \ #define OP_LD_ATOMIC(insn,fname) \
static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
@ -1626,12 +1597,12 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
switch (opc) { switch (opc) {
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_LWU: case OPC_LWU:
op_ld_lwu(t0, t0, ctx); tcg_gen_qemu_ld32u(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "lwu"; opn = "lwu";
break; break;
case OPC_LD: case OPC_LD:
op_ld_ld(t0, t0, ctx); tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "ld"; opn = "ld";
break; break;
@ -1658,7 +1629,7 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
case OPC_LDPC: case OPC_LDPC:
tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
op_ld_ld(t0, t0, ctx); tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "ldpc"; opn = "ldpc";
break; break;
@ -1666,32 +1637,32 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
case OPC_LWPC: case OPC_LWPC:
tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
op_ld_lw(t0, t0, ctx); tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "lwpc"; opn = "lwpc";
break; break;
case OPC_LW: case OPC_LW:
op_ld_lw(t0, t0, ctx); tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "lw"; opn = "lw";
break; break;
case OPC_LH: case OPC_LH:
op_ld_lh(t0, t0, ctx); tcg_gen_qemu_ld16s(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "lh"; opn = "lh";
break; break;
case OPC_LHU: case OPC_LHU:
op_ld_lhu(t0, t0, ctx); tcg_gen_qemu_ld16u(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "lhu"; opn = "lhu";
break; break;
case OPC_LB: case OPC_LB:
op_ld_lb(t0, t0, ctx); tcg_gen_qemu_ld8s(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "lb"; opn = "lb";
break; break;
case OPC_LBU: case OPC_LBU:
op_ld_lbu(t0, t0, ctx); tcg_gen_qemu_ld8u(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "lbu"; opn = "lbu";
break; break;
@ -1735,7 +1706,7 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
switch (opc) { switch (opc) {
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_SD: case OPC_SD:
op_st_sd(t1, t0, ctx); tcg_gen_qemu_st64(t1, t0, ctx->mem_idx);
opn = "sd"; opn = "sd";
break; break;
case OPC_SDL: case OPC_SDL:
@ -1750,15 +1721,15 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
break; break;
#endif #endif
case OPC_SW: case OPC_SW:
op_st_sw(t1, t0, ctx); tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
opn = "sw"; opn = "sw";
break; break;
case OPC_SH: case OPC_SH:
op_st_sh(t1, t0, ctx); tcg_gen_qemu_st16(t1, t0, ctx->mem_idx);
opn = "sh"; opn = "sh";
break; break;
case OPC_SB: case OPC_SB:
op_st_sb(t1, t0, ctx); tcg_gen_qemu_st8(t1, t0, ctx->mem_idx);
opn = "sb"; opn = "sb";
break; break;
case OPC_SWL: case OPC_SWL:
@ -9320,22 +9291,22 @@ static void gen_mips16_save (DisasContext *ctx,
case 4: case 4:
gen_base_offset_addr(ctx, t0, 29, 12); gen_base_offset_addr(ctx, t0, 29, 12);
gen_load_gpr(t1, 7); gen_load_gpr(t1, 7);
op_st_sw(t1, t0, ctx); tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
/* Fall through */ /* Fall through */
case 3: case 3:
gen_base_offset_addr(ctx, t0, 29, 8); gen_base_offset_addr(ctx, t0, 29, 8);
gen_load_gpr(t1, 6); gen_load_gpr(t1, 6);
op_st_sw(t1, t0, ctx); tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
/* Fall through */ /* Fall through */
case 2: case 2:
gen_base_offset_addr(ctx, t0, 29, 4); gen_base_offset_addr(ctx, t0, 29, 4);
gen_load_gpr(t1, 5); gen_load_gpr(t1, 5);
op_st_sw(t1, t0, ctx); tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
/* Fall through */ /* Fall through */
case 1: case 1:
gen_base_offset_addr(ctx, t0, 29, 0); gen_base_offset_addr(ctx, t0, 29, 0);
gen_load_gpr(t1, 4); gen_load_gpr(t1, 4);
op_st_sw(t1, t0, ctx); tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
} }
gen_load_gpr(t0, 29); gen_load_gpr(t0, 29);
@ -9343,7 +9314,7 @@ static void gen_mips16_save (DisasContext *ctx,
#define DECR_AND_STORE(reg) do { \ #define DECR_AND_STORE(reg) do { \
tcg_gen_subi_tl(t0, t0, 4); \ tcg_gen_subi_tl(t0, t0, 4); \
gen_load_gpr(t1, reg); \ gen_load_gpr(t1, reg); \
op_st_sw(t1, t0, ctx); \ tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); \
} while (0) } while (0)
if (do_ra) { if (do_ra) {
@ -9441,10 +9412,10 @@ static void gen_mips16_restore (DisasContext *ctx,
tcg_gen_addi_tl(t0, cpu_gpr[29], framesize); tcg_gen_addi_tl(t0, cpu_gpr[29], framesize);
#define DECR_AND_LOAD(reg) do { \ #define DECR_AND_LOAD(reg) do { \
tcg_gen_subi_tl(t0, t0, 4); \ tcg_gen_subi_tl(t0, t0, 4); \
op_ld_lw(t1, t0, ctx); \ tcg_gen_qemu_ld32u(t1, t0, ctx->mem_idx); \
gen_store_gpr(t1, reg); \ gen_store_gpr(t1, reg); \
} while (0) } while (0)
if (do_ra) { if (do_ra) {
@ -10950,7 +10921,7 @@ static void gen_ldxs (DisasContext *ctx, int base, int index, int rd)
gen_op_addr_add(ctx, t0, t1, t0); gen_op_addr_add(ctx, t0, t1, t0);
} }
op_ld_lw(t1, t0, ctx); tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rd); gen_store_gpr(t1, rd);
tcg_temp_free(t0); tcg_temp_free(t0);
@ -10979,21 +10950,21 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
generate_exception(ctx, EXCP_RI); generate_exception(ctx, EXCP_RI);
return; return;
} }
op_ld_lw(t1, t0, ctx); tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rd); gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 4); tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
op_ld_lw(t1, t0, ctx); tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rd+1); gen_store_gpr(t1, rd+1);
opn = "lwp"; opn = "lwp";
break; break;
case SWP: case SWP:
gen_load_gpr(t1, rd); gen_load_gpr(t1, rd);
op_st_sw(t1, t0, ctx); tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
tcg_gen_movi_tl(t1, 4); tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd+1); gen_load_gpr(t1, rd+1);
op_st_sw(t1, t0, ctx); tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
opn = "swp"; opn = "swp";
break; break;
#ifdef TARGET_MIPS64 #ifdef TARGET_MIPS64
@ -11002,21 +10973,21 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
generate_exception(ctx, EXCP_RI); generate_exception(ctx, EXCP_RI);
return; return;
} }
op_ld_ld(t1, t0, ctx); tcg_gen_qemu_ld64(t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rd); gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 8); tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
op_ld_ld(t1, t0, ctx); tcg_gen_qemu_ld64(t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rd+1); gen_store_gpr(t1, rd+1);
opn = "ldp"; opn = "ldp";
break; break;
case SDP: case SDP:
gen_load_gpr(t1, rd); gen_load_gpr(t1, rd);
op_st_sd(t1, t0, ctx); tcg_gen_qemu_st64(t1, t0, ctx->mem_idx);
tcg_gen_movi_tl(t1, 8); tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd+1); gen_load_gpr(t1, rd+1);
op_st_sd(t1, t0, ctx); tcg_gen_qemu_st64(t1, t0, ctx->mem_idx);
opn = "sdp"; opn = "sdp";
break; break;
#endif #endif
@ -12654,23 +12625,23 @@ static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
switch (opc) { switch (opc) {
case OPC_LBUX: case OPC_LBUX:
op_ld_lbu(t0, t0, ctx); tcg_gen_qemu_ld8u(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
opn = "lbux"; opn = "lbux";
break; break;
case OPC_LHX: case OPC_LHX:
op_ld_lh(t0, t0, ctx); tcg_gen_qemu_ld16s(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
opn = "lhx"; opn = "lhx";
break; break;
case OPC_LWX: case OPC_LWX:
op_ld_lw(t0, t0, ctx); tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
opn = "lwx"; opn = "lwx";
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_LDX: case OPC_LDX:
op_ld_ld(t0, t0, ctx); tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rd); gen_store_gpr(t0, rd);
opn = "ldx"; opn = "ldx";
break; break;