target-ppc: Introduce DFP Convert to Long/Extended
Add emulation of the PowerPC Convert to DFP Long (dctdp[.]) and Convert to DFP Extended (dctqpq[.]) instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -286,6 +286,15 @@ static void dfp_check_for_VXSNAN(struct PPC_DFP *dfp)
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}
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}
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static void dfp_check_for_VXSNAN_and_convert_to_QNaN(struct PPC_DFP *dfp)
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{
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if (decNumberIsSNaN(&dfp->t)) {
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dfp->t.bits &= ~DECSNAN;
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dfp->t.bits |= DECNAN;
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dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXSNAN, FP_VE);
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}
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}
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static void dfp_check_for_VXISI(struct PPC_DFP *dfp, int testForSameSign)
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{
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if (dfp->context.status & DEC_Invalid_operation) {
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@ -840,3 +849,27 @@ static void RINTN_PPs(struct PPC_DFP *dfp)
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DFP_HELPER_RINT(drintn, RINTN_PPs, 64)
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DFP_HELPER_RINT(drintnq, RINTN_PPs, 128)
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void helper_dctdp(CPUPPCState *env, uint64_t *t, uint64_t *b)
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{
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struct PPC_DFP dfp;
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uint32_t b_short = *b;
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dfp_prepare_decimal64(&dfp, 0, 0, env);
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decimal32ToNumber((decimal32 *)&b_short, &dfp.t);
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decimal64FromNumber((decimal64 *)t, &dfp.t, &dfp.context);
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dfp_set_FPRF_from_FRT(&dfp);
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}
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void helper_dctqpq(CPUPPCState *env, uint64_t *t, uint64_t *b)
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{
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struct PPC_DFP dfp;
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dfp_prepare_decimal128(&dfp, 0, 0, env);
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decimal64ToNumber((decimal64 *)b, &dfp.t);
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dfp_check_for_VXSNAN_and_convert_to_QNaN(&dfp);
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dfp_set_FPRF_from_FRT(&dfp);
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decimal128FromNumber((decimal128 *)&dfp.t64, &dfp.t, &dfp.context);
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t[0] = dfp.t64[HI_IDX];
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t[1] = dfp.t64[LO_IDX];
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}
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@ -646,3 +646,5 @@ DEF_HELPER_5(drintx, void, env, fprp, fprp, i32, i32)
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DEF_HELPER_5(drintxq, void, env, fprp, fprp, i32, i32)
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DEF_HELPER_5(drintn, void, env, fprp, fprp, i32, i32)
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DEF_HELPER_5(drintnq, void, env, fprp, fprp, i32, i32)
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DEF_HELPER_3(dctdp, void, env, fprp, fprp)
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DEF_HELPER_3(dctqpq, void, env, fprp, fprp)
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@ -8386,6 +8386,8 @@ GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
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GEN_DFP_T_B_Rc(dctdp)
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GEN_DFP_T_B_Rc(dctqpq)
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/*** SPE extension ***/
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/* Register moves */
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@ -11343,6 +11345,8 @@ GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
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GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
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GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
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GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
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GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
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GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
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#undef GEN_SPE
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#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
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GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
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