hw: timer: ibex_timer: Fixup reading w/o register
This change fixes a bug where a write only register is read. As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table the 'INTR_TEST0' register is write only. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220110051606.4031241-1-alistair.francis@opensource.wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -130,7 +130,6 @@ static void ibex_timer_reset(DeviceState *dev)
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s->timer_compare_upper0 = 0xFFFFFFFF;
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s->timer_intr_enable = 0x00000000;
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s->timer_intr_state = 0x00000000;
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s->timer_intr_test = 0x00000000;
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ibex_timer_update_irqs(s);
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}
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@ -168,7 +167,8 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
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retvalue = s->timer_intr_state;
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break;
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case R_INTR_TEST:
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retvalue = s->timer_intr_test;
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qemu_log_mask(LOG_GUEST_ERROR,
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"Attempted to read INTR_TEST, a write only register");
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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@ -215,10 +215,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr,
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s->timer_intr_state &= ~val;
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break;
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case R_INTR_TEST:
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s->timer_intr_test = val;
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if (s->timer_intr_enable &
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s->timer_intr_test &
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R_INTR_ENABLE_IE_0_MASK) {
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if (s->timer_intr_enable & val & R_INTR_ENABLE_IE_0_MASK) {
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s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
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qemu_set_irq(s->irq, true);
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}
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@ -247,8 +244,8 @@ static int ibex_timer_post_load(void *opaque, int version_id)
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static const VMStateDescription vmstate_ibex_timer = {
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.name = TYPE_IBEX_TIMER,
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.version_id = 1,
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.minimum_version_id = 1,
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.version_id = 2,
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.minimum_version_id = 2,
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.post_load = ibex_timer_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(timer_ctrl, IbexTimerState),
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@ -257,7 +254,6 @@ static const VMStateDescription vmstate_ibex_timer = {
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VMSTATE_UINT32(timer_compare_upper0, IbexTimerState),
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VMSTATE_UINT32(timer_intr_enable, IbexTimerState),
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VMSTATE_UINT32(timer_intr_state, IbexTimerState),
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VMSTATE_UINT32(timer_intr_test, IbexTimerState),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -43,7 +43,6 @@ struct IbexTimerState {
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uint32_t timer_compare_upper0;
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uint32_t timer_intr_enable;
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uint32_t timer_intr_state;
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uint32_t timer_intr_test;
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uint32_t timebase_freq;
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