hw/nios2: Machine with a Vectored Interrupt Controller

Demonstrate how to use nios2 VIC on a machine.
Introduce a new machine property to attach a VIC.

When VIC is present, let the CPU know that it should use the
External Interrupt Interface instead of the Internal Interrupt Interface.
The devices on the machine are attached to the VIC and not directly to cpu.
To allow VIC update EIC fields, we set the "cpu" property of the VIC
with a reference to the nios2 cpu.

[rth: Put a property on the 10m50-ghrd machine, rather than
      create a new machine class.]

Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai>
Message-Id: <20220303153906.2024748-6-amir.gonnen@neuroblade.ai>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220421151735.31996-63-richard.henderson@linaro.org>
This commit is contained in:
Amir Gonnen 2022-04-21 08:17:33 -07:00 committed by Richard Henderson
parent e734cedf11
commit 28a3c1b5f1
2 changed files with 53 additions and 9 deletions

View File

@ -27,6 +27,7 @@
#include "hw/sysbus.h" #include "hw/sysbus.h"
#include "hw/char/serial.h" #include "hw/char/serial.h"
#include "hw/intc/nios2_vic.h"
#include "hw/qdev-properties.h" #include "hw/qdev-properties.h"
#include "sysemu/sysemu.h" #include "sysemu/sysemu.h"
#include "hw/boards.h" #include "hw/boards.h"
@ -43,6 +44,8 @@ struct Nios2MachineState {
MemoryRegion phys_tcm_alias; MemoryRegion phys_tcm_alias;
MemoryRegion phys_ram; MemoryRegion phys_ram;
MemoryRegion phys_ram_alias; MemoryRegion phys_ram_alias;
bool vic;
}; };
#define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd") #define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd")
@ -81,10 +84,39 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base, memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base,
&nms->phys_ram_alias); &nms->phys_ram_alias);
/* Create CPU -- FIXME */ /* Create CPU. We need to set eic_present between init and realize. */
cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); cpu = NIOS2_CPU(object_new(TYPE_NIOS2_CPU));
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); /* Enable the External Interrupt Controller within the CPU. */
cpu->eic_present = nms->vic;
/* Configure new exception vectors. */
cpu->reset_addr = 0xd4000000;
cpu->exception_addr = 0xc8000120;
cpu->fast_tlb_miss_addr = 0xc0000100;
qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
if (nms->vic) {
DeviceState *dev = qdev_new(TYPE_NIOS2_VIC);
MemoryRegion *dev_mr;
qemu_irq cpu_irq;
object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
cpu_irq = qdev_get_gpio_in_named(DEVICE(cpu), "EIC", 0);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq);
for (int i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(dev, i);
}
dev_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
memory_region_add_subregion(address_space_mem, 0x18002000, dev_mr);
} else {
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i);
}
} }
/* Register: Altera 16550 UART */ /* Register: Altera 16550 UART */
@ -105,15 +137,22 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]);
/* Configure new exception vectors and reset CPU for it to take effect. */
cpu->reset_addr = 0xd4000000;
cpu->exception_addr = 0xc8000120;
cpu->fast_tlb_miss_addr = 0xc0000100;
nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename, nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename,
BINARY_DEVICE_TREE_FILE, NULL); BINARY_DEVICE_TREE_FILE, NULL);
} }
static bool get_vic(Object *obj, Error **errp)
{
Nios2MachineState *nms = NIOS2_MACHINE(obj);
return nms->vic;
}
static void set_vic(Object *obj, bool value, Error **errp)
{
Nios2MachineState *nms = NIOS2_MACHINE(obj);
nms->vic = value;
}
static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data) static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data)
{ {
MachineClass *mc = MACHINE_CLASS(oc); MachineClass *mc = MACHINE_CLASS(oc);
@ -121,6 +160,10 @@ static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data)
mc->desc = "Altera 10M50 GHRD Nios II design"; mc->desc = "Altera 10M50 GHRD Nios II design";
mc->init = nios2_10m50_ghrd_init; mc->init = nios2_10m50_ghrd_init;
mc->is_default = true; mc->is_default = true;
object_class_property_add_bool(oc, "vic", get_vic, set_vic);
object_class_property_set_description(oc, "vic",
"Set on/off to enable/disable the Vectored Interrupt Controller");
} }
static const TypeInfo nios2_10m50_ghrd_type_info = { static const TypeInfo nios2_10m50_ghrd_type_info = {

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@ -3,6 +3,7 @@ config NIOS2_10M50
select NIOS2 select NIOS2
select SERIAL select SERIAL
select ALTERA_TIMER select ALTERA_TIMER
select NIOS2_VIC
config NIOS2_GENERIC_NOMMU config NIOS2_GENERIC_NOMMU
bool bool