From 28930245a823c3e452d65523c9ad01f56801df72 Mon Sep 17 00:00:00 2001 From: Fabiano Rosas Date: Fri, 18 Feb 2022 08:34:15 +0100 Subject: [PATCH] target/ppc: cpu_init: Move 755 L2 cache SPRs into a function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is just to have 755-specific registers contained into a function, intead of leaving them open-coded in init_proc_755. It makes init_proc easier to read and keeps later patches that touch this code a bit cleaner. Signed-off-by: Fabiano Rosas Reviewed-by: David Gibson Message-Id: <20220216162426.1885923-16-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu_init.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index d5c23785d7..ef9353a7fe 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -503,6 +503,20 @@ static void register_745_sprs(CPUPPCState *env) 0x00000000); } +static void register_755_sprs(CPUPPCState *env) +{ + /* L2 cache control */ + spr_register(env, SPR_L2CR, "L2CR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, spr_access_nop, + 0x00000000); + + spr_register(env, SPR_L2PMCR, "L2PMCR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +} + /* SPR common to all 7xx PowerPC implementations */ static void register_7xx_sprs(CPUPPCState *env) { @@ -4545,16 +4559,8 @@ static void init_proc_755(CPUPPCState *env) register_sdr1_sprs(env); register_7xx_sprs(env); register_745_sprs(env); - /* L2 cache control */ - spr_register(env, SPR_L2CR, "L2CR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, spr_access_nop, - 0x00000000); + register_755_sprs(env); - spr_register(env, SPR_L2PMCR, "L2PMCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); /* Thermal management */ register_thrm_sprs(env);