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qemu-macppc patches for 8.0

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Merge tag 'qemu-macppc-20230206' of https://github.com/mcayland/qemu into staging

qemu-macppc patches for 8.0

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# gpg: Signature made Mon 06 Feb 2023 22:01:34 GMT
# gpg:                using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg:                issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* tag 'qemu-macppc-20230206' of https://github.com/mcayland/qemu:
  mac_oldworld: Allow specifying nvram backing store
  mac_nvram: Add block backend to persist NVRAM contents
  hw/misc/macio: Return bool from functions taking errp
  hw/misc/macio: Remove some single use local variables
  hw/misc/macio: Rename sysbus_dev to sbd for consistency and brevity
  hw/misc/macio: Avoid some QOM casts
  mac_{old,new}world: Use local variable instead of qdev_get_machine()
  input/adb: Only include header where needed

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-02-07 11:00:25 +00:00
commit 285ee77f5b
12 changed files with 114 additions and 108 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/misc/macio/cuda.c
View File

@ -27,8 +27,6 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "hw/input/adb.h"
#include "hw/misc/mos6522.h"
#include "hw/misc/macio/cuda.h"
#include "qapi/error.h"
#include "qemu/timer.h"

151
hw/misc/macio/macio.c
View File

@ -53,10 +53,8 @@
*/
static void macio_escc_legacy_setup(MacIOState *s)
{
ESCCState *escc = ESCC(&s->escc);
SysBusDevice *sbd = SYS_BUS_DEVICE(escc);
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->escc);
MemoryRegion *escc_legacy = g_new(MemoryRegion, 1);
MemoryRegion *bar = &s->bar;
int i;
static const int maps[] = {
0x00, 0x00, /* Command B */
@ -80,30 +78,29 @@ static void macio_escc_legacy_setup(MacIOState *s)
memory_region_add_subregion(escc_legacy, maps[i], port);
}
memory_region_add_subregion(bar, 0x12000, escc_legacy);
memory_region_add_subregion(&s->bar, 0x12000, escc_legacy);
}
static void macio_bar_setup(MacIOState *s)
{
ESCCState *escc = ESCC(&s->escc);
SysBusDevice *sbd = SYS_BUS_DEVICE(escc);
MemoryRegion *bar = &s->bar;
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->escc);
MemoryRegion *bar = sysbus_mmio_get_region(sbd, 0);
memory_region_add_subregion(bar, 0x13000, sysbus_mmio_get_region(sbd, 0));
memory_region_add_subregion(&s->bar, 0x13000, bar);
macio_escc_legacy_setup(s);
}
static void macio_common_realize(PCIDevice *d, Error **errp)
static bool macio_common_realize(PCIDevice *d, Error **errp)
{
MacIOState *s = MACIO(d);
SysBusDevice *sysbus_dev;
SysBusDevice *sbd;
if (!qdev_realize(DEVICE(&s->dbdma), BUS(&s->macio_bus), errp)) {
return;
return false;
}
sysbus_dev = SYS_BUS_DEVICE(&s->dbdma);
sbd = SYS_BUS_DEVICE(&s->dbdma);
memory_region_add_subregion(&s->bar, 0x08000,
sysbus_mmio_get_region(sysbus_dev, 0));
sysbus_mmio_get_region(sbd, 0));
qdev_prop_set_uint32(DEVICE(&s->escc), "disabled", 0);
qdev_prop_set_uint32(DEVICE(&s->escc), "frequency", ESCC_CLOCK);
@ -111,28 +108,29 @@ static void macio_common_realize(PCIDevice *d, Error **errp)
qdev_prop_set_uint32(DEVICE(&s->escc), "chnBtype", escc_serial);
qdev_prop_set_uint32(DEVICE(&s->escc), "chnAtype", escc_serial);
if (!qdev_realize(DEVICE(&s->escc), BUS(&s->macio_bus), errp)) {
return;
return false;
}
macio_bar_setup(s);
pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar);
return true;
}
static void macio_realize_ide(MacIOState *s, MACIOIDEState *ide,
static bool macio_realize_ide(MacIOState *s, MACIOIDEState *ide,
qemu_irq irq0, qemu_irq irq1, int dmaid,
Error **errp)
{
SysBusDevice *sysbus_dev;
SysBusDevice *sbd = SYS_BUS_DEVICE(ide);
sysbus_dev = SYS_BUS_DEVICE(ide);
sysbus_connect_irq(sysbus_dev, 0, irq0);
sysbus_connect_irq(sysbus_dev, 1, irq1);
sysbus_connect_irq(sbd, 0, irq0);
sysbus_connect_irq(sbd, 1, irq1);
qdev_prop_set_uint32(DEVICE(ide), "channel", dmaid);
object_property_set_link(OBJECT(ide), "dbdma", OBJECT(&s->dbdma),
&error_abort);
macio_ide_register_dma(ide);
qdev_realize(DEVICE(ide), BUS(&s->macio_bus), errp);
return qdev_realize(DEVICE(ide), BUS(&s->macio_bus), errp);
}
static void macio_oldworld_realize(PCIDevice *d, Error **errp)
@ -140,12 +138,9 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp)
MacIOState *s = MACIO(d);
OldWorldMacIOState *os = OLDWORLD_MACIO(d);
DeviceState *pic_dev = DEVICE(&os->pic);
Error *err = NULL;
SysBusDevice *sysbus_dev;
SysBusDevice *sbd;
macio_common_realize(d, &err);
if (err) {
error_propagate(errp, err);
if (!macio_common_realize(d, errp)) {
return;
}
@ -153,51 +148,44 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp)
if (!qdev_realize(DEVICE(&os->pic), BUS(&s->macio_bus), errp)) {
return;
}
sysbus_dev = SYS_BUS_DEVICE(&os->pic);
sbd = SYS_BUS_DEVICE(&os->pic);
memory_region_add_subregion(&s->bar, 0x0,
sysbus_mmio_get_region(sysbus_dev, 0));
sysbus_mmio_get_region(sbd, 0));
qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
s->frequency);
if (!qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), errp)) {
return;
}
sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
sbd = SYS_BUS_DEVICE(&s->cuda);
memory_region_add_subregion(&s->bar, 0x16000,
sysbus_mmio_get_region(sysbus_dev, 0));
sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
OLDWORLD_CUDA_IRQ));
sysbus_mmio_get_region(sbd, 0));
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(pic_dev, OLDWORLD_CUDA_IRQ));
sysbus_dev = SYS_BUS_DEVICE(&s->escc);
sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
OLDWORLD_ESCCB_IRQ));
sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev,
OLDWORLD_ESCCA_IRQ));
sbd = SYS_BUS_DEVICE(&s->escc);
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(pic_dev, OLDWORLD_ESCCB_IRQ));
sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(pic_dev, OLDWORLD_ESCCA_IRQ));
if (!qdev_realize(DEVICE(&os->nvram), BUS(&s->macio_bus), errp)) {
return;
}
sysbus_dev = SYS_BUS_DEVICE(&os->nvram);
sbd = SYS_BUS_DEVICE(&os->nvram);
memory_region_add_subregion(&s->bar, 0x60000,
sysbus_mmio_get_region(sysbus_dev, 0));
sysbus_mmio_get_region(sbd, 0));
pmac_format_nvram_partition(&os->nvram, os->nvram.size);
/* IDE buses */
macio_realize_ide(s, &os->ide[0],
if (!macio_realize_ide(s, &os->ide[0],
qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ),
qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_DMA_IRQ),
0x16, &err);
if (err) {
error_propagate(errp, err);
0x16, errp)) {
return;
}
macio_realize_ide(s, &os->ide[1],
if (!macio_realize_ide(s, &os->ide[1],
qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_IRQ),
qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_DMA_IRQ),
0x1a, &err);
if (err) {
error_propagate(errp, err);
0x1a, errp)) {
return;
}
}
@ -220,11 +208,11 @@ static void macio_oldworld_init(Object *obj)
DeviceState *dev;
int i;
object_initialize_child(OBJECT(s), "pic", &os->pic, TYPE_HEATHROW);
object_initialize_child(obj, "pic", &os->pic, TYPE_HEATHROW);
object_initialize_child(OBJECT(s), "cuda", &s->cuda, TYPE_CUDA);
object_initialize_child(obj, "cuda", &s->cuda, TYPE_CUDA);
object_initialize_child(OBJECT(s), "nvram", &os->nvram, TYPE_MACIO_NVRAM);
object_initialize_child(obj, "nvram", &os->nvram, TYPE_MACIO_NVRAM);
dev = DEVICE(&os->nvram);
qdev_prop_set_uint32(dev, "size", MACIO_NVRAM_SIZE);
qdev_prop_set_uint32(dev, "it_shift", 4);
@ -273,45 +261,36 @@ static void macio_newworld_realize(PCIDevice *d, Error **errp)
MacIOState *s = MACIO(d);
NewWorldMacIOState *ns = NEWWORLD_MACIO(d);
DeviceState *pic_dev = DEVICE(&ns->pic);
Error *err = NULL;
SysBusDevice *sysbus_dev;
SysBusDevice *sbd;
MemoryRegion *timer_memory = NULL;
macio_common_realize(d, &err);
if (err) {
error_propagate(errp, err);
if (!macio_common_realize(d, errp)) {
return;
}
/* OpenPIC */
qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO);
sysbus_dev = SYS_BUS_DEVICE(&ns->pic);
sysbus_realize_and_unref(sysbus_dev, &error_fatal);
sbd = SYS_BUS_DEVICE(&ns->pic);
sysbus_realize_and_unref(sbd, &error_fatal);
memory_region_add_subregion(&s->bar, 0x40000,
sysbus_mmio_get_region(sysbus_dev, 0));
sysbus_mmio_get_region(sbd, 0));
sysbus_dev = SYS_BUS_DEVICE(&s->escc);
sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
NEWWORLD_ESCCB_IRQ));
sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev,
NEWWORLD_ESCCA_IRQ));
sbd = SYS_BUS_DEVICE(&s->escc);
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(pic_dev, NEWWORLD_ESCCB_IRQ));
sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(pic_dev, NEWWORLD_ESCCA_IRQ));
/* IDE buses */
macio_realize_ide(s, &ns->ide[0],
if (!macio_realize_ide(s, &ns->ide[0],
qdev_get_gpio_in(pic_dev, NEWWORLD_IDE0_IRQ),
qdev_get_gpio_in(pic_dev, NEWWORLD_IDE0_DMA_IRQ),
0x16, &err);
if (err) {
error_propagate(errp, err);
0x16, errp)) {
return;
}
macio_realize_ide(s, &ns->ide[1],
if (!macio_realize_ide(s, &ns->ide[1],
qdev_get_gpio_in(pic_dev, NEWWORLD_IDE1_IRQ),
qdev_get_gpio_in(pic_dev, NEWWORLD_IDE1_DMA_IRQ),
0x1a, &err);
if (err) {
error_propagate(errp, err);
0x1a, errp)) {
return;
}
@ -326,27 +305,26 @@ static void macio_newworld_realize(PCIDevice *d, Error **errp)
if (!qdev_realize(DEVICE(&ns->gpio), BUS(&s->macio_bus), errp)) {
return;
}
sysbus_dev = SYS_BUS_DEVICE(&ns->gpio);
sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev,
sbd = SYS_BUS_DEVICE(&ns->gpio);
sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(pic_dev,
NEWWORLD_EXTING_GPIO1));
sysbus_connect_irq(sysbus_dev, 9, qdev_get_gpio_in(pic_dev,
sysbus_connect_irq(sbd, 9, qdev_get_gpio_in(pic_dev,
NEWWORLD_EXTING_GPIO9));
memory_region_add_subregion(&s->bar, 0x50,
sysbus_mmio_get_region(sysbus_dev, 0));
sysbus_mmio_get_region(sbd, 0));
/* PMU */
object_initialize_child(OBJECT(s), "pmu", &s->pmu, TYPE_VIA_PMU);
object_property_set_link(OBJECT(&s->pmu), "gpio", OBJECT(sysbus_dev),
object_property_set_link(OBJECT(&s->pmu), "gpio", OBJECT(sbd),
&error_abort);
qdev_prop_set_bit(DEVICE(&s->pmu), "has-adb", ns->has_adb);
if (!qdev_realize(DEVICE(&s->pmu), BUS(&s->macio_bus), errp)) {
return;
}
sysbus_dev = SYS_BUS_DEVICE(&s->pmu);
sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
NEWWORLD_PMU_IRQ));
sbd = SYS_BUS_DEVICE(&s->pmu);
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(pic_dev, NEWWORLD_PMU_IRQ));
memory_region_add_subregion(&s->bar, 0x16000,
sysbus_mmio_get_region(sysbus_dev, 0));
sysbus_mmio_get_region(sbd, 0));
} else {
object_unparent(OBJECT(&ns->gpio));
@ -358,11 +336,10 @@ static void macio_newworld_realize(PCIDevice *d, Error **errp)
if (!qdev_realize(DEVICE(&s->cuda), BUS(&s->macio_bus), errp)) {
return;
}
sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
NEWWORLD_CUDA_IRQ));
sbd = SYS_BUS_DEVICE(&s->cuda);
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(pic_dev, NEWWORLD_CUDA_IRQ));
memory_region_add_subregion(&s->bar, 0x16000,
sysbus_mmio_get_region(sysbus_dev, 0));
sysbus_mmio_get_region(sbd, 0));
}
}
@ -372,9 +349,9 @@ static void macio_newworld_init(Object *obj)
NewWorldMacIOState *ns = NEWWORLD_MACIO(obj);
int i;
object_initialize_child(OBJECT(s), "pic", &ns->pic, TYPE_OPENPIC);
object_initialize_child(obj, "pic", &ns->pic, TYPE_OPENPIC);
object_initialize_child(OBJECT(s), "gpio", &ns->gpio, TYPE_MACIO_GPIO);
object_initialize_child(obj, "gpio", &ns->gpio, TYPE_MACIO_GPIO);
for (i = 0; i < 2; i++) {
macio_init_ide(s, &ns->ide[i], i);
@ -390,9 +367,9 @@ static void macio_instance_init(Object *obj)
qbus_init(&s->macio_bus, sizeof(s->macio_bus), TYPE_MACIO_BUS,
DEVICE(obj), "macio.0");
object_initialize_child(OBJECT(s), "dbdma", &s->dbdma, TYPE_MAC_DBDMA);
object_initialize_child(obj, "dbdma", &s->dbdma, TYPE_MAC_DBDMA);
object_initialize_child(OBJECT(s), "escc", &s->escc, TYPE_ESCC);
object_initialize_child(obj, "escc", &s->escc, TYPE_ESCC);
}
static const VMStateDescription vmstate_macio_oldworld = {

3
hw/misc/macio/pmu.c
View File

@ -31,10 +31,7 @@
#include "qemu/osdep.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "hw/input/adb.h"
#include "hw/irq.h"
#include "hw/misc/mos6522.h"
#include "hw/misc/macio/gpio.h"
#include "hw/misc/macio/pmu.h"
#include "qapi/error.h"
#include "qemu/timer.h"

1
hw/misc/mos6522.c
View File

@ -25,7 +25,6 @@
*/
#include "qemu/osdep.h"
#include "hw/input/adb.h"
#include "hw/irq.h"
#include "hw/misc/mos6522.h"
#include "hw/qdev-properties.h"

28
hw/nvram/mac_nvram.c
View File

@ -24,9 +24,12 @@
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/nvram/chrp_nvram.h"
#include "hw/nvram/mac_nvram.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "sysemu/block-backend.h"
#include "migration/vmstate.h"
#include "qemu/cutils.h"
#include "qemu/module.h"
@ -44,6 +47,9 @@ static void macio_nvram_writeb(void *opaque, hwaddr addr,
addr = (addr >> s->it_shift) & (s->size - 1);
trace_macio_nvram_write(addr, value);
s->data[addr] = value;
if (s->blk) {
blk_pwrite(s->blk, addr, 1, &s->data[addr], 0);
}
}
static uint64_t macio_nvram_readb(void *opaque, hwaddr addr,
@ -91,6 +97,27 @@ static void macio_nvram_realizefn(DeviceState *dev, Error **errp)
s->data = g_malloc0(s->size);
if (s->blk) {
int64_t len = blk_getlength(s->blk);
if (len < 0) {
error_setg_errno(errp, -len,
"could not get length of nvram backing image");
return;
} else if (len != s->size) {
error_setg_errno(errp, -len,
"invalid size nvram backing image");
return;
}
if (blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
BLK_PERM_ALL, errp) < 0) {
return;
}
if (blk_pread(s->blk, 0, s->size, s->data, 0) < 0) {
error_setg(errp, "can't read-nvram contents");
return;
}
}
memory_region_init_io(&s->mem, OBJECT(s), &macio_nvram_ops, s,
"macio-nvram", s->size << s->it_shift);
sysbus_init_mmio(d, &s->mem);
@ -106,6 +133,7 @@ static void macio_nvram_unrealizefn(DeviceState *dev)
static Property macio_nvram_properties[] = {
DEFINE_PROP_UINT32("size", MacIONVRAMState, size, 0),
DEFINE_PROP_UINT32("it_shift", MacIONVRAMState, it_shift, 0),
DEFINE_PROP_DRIVE("drive", MacIONVRAMState, blk),
DEFINE_PROP_END_OF_LIST()
};

3
hw/ppc/mac_newworld.c
View File

@ -466,8 +466,7 @@ static void ppc_core99_init(MachineState *machine)
fw_cfg = FW_CFG(dev);
qdev_prop_set_uint32(dev, "data_width", 1);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg));
object_property_add_child(OBJECT(machine), TYPE_FW_CFG, OBJECT(fw_cfg));
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, CFG_ADDR);

11
hw/ppc/mac_oldworld.c
View File

@ -102,7 +102,7 @@ static void ppc_heathrow_init(MachineState *machine)
DeviceState *dev, *pic_dev, *grackle_dev;
BusState *adb_bus;
uint16_t ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DriveInfo *dinfo, *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
void *fw_cfg;
uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ;
@ -245,6 +245,12 @@ static void ppc_heathrow_init(MachineState *machine)
qdev_prop_set_chr(dev, "chrA", serial_hd(0));
qdev_prop_set_chr(dev, "chrB", serial_hd(1));
dinfo = drive_get(IF_MTD, 0, 0);
if (dinfo) {
dev = DEVICE(object_resolve_path_component(macio, "nvram"));
qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
}
pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal);
pic_dev = DEVICE(object_resolve_path_component(macio, "pic"));
@ -303,8 +309,7 @@ static void ppc_heathrow_init(MachineState *machine)
fw_cfg = FW_CFG(dev);
qdev_prop_set_uint32(dev, "data_width", 1);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg));
object_property_add_child(OBJECT(machine), TYPE_FW_CFG, OBJECT(fw_cfg));
s = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(s, &error_fatal);
sysbus_mmio_map(s, 0, CFG_ADDR);

1
include/hw/misc/mac_via.h
View File

@ -12,6 +12,7 @@
#include "exec/memory.h"
#include "hw/sysbus.h"
#include "hw/misc/mos6522.h"
#include "hw/input/adb.h"
#include "qom/object.h"

1
include/hw/misc/macio/cuda.h
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@ -26,6 +26,7 @@
#ifndef CUDA_H
#define CUDA_H
#include "hw/input/adb.h"
#include "hw/misc/mos6522.h"
#include "qom/object.h"

1
include/hw/misc/macio/pmu.h
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@ -10,6 +10,7 @@
#ifndef PMU_H
#define PMU_H
#include "hw/input/adb.h"
#include "hw/misc/mos6522.h"
#include "hw/misc/macio/gpio.h"
#include "qom/object.h"

3
include/hw/misc/mos6522.h
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@ -27,9 +27,8 @@
#ifndef MOS6522_H
#define MOS6522_H
#include "exec/memory.h"
#include "exec/hwaddr.h"
#include "hw/sysbus.h"
#include "hw/input/adb.h"
#include "qom/object.h"
#define MOS6522_NUM_REGS 16

1
include/hw/nvram/mac_nvram.h
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@ -44,6 +44,7 @@ struct MacIONVRAMState {
MemoryRegion mem;
uint8_t *data;
BlockBackend *blk;
};
void pmac_format_nvram_partition(MacIONVRAMState *nvr, int len);