mirror of https://gitlab.com/qemu-project/qemu
tests/qtest: Fix STM32L4x5 GPIO test on 32-bit
The test mangles the GPIO address and the pin number in the
qtest_add_data_func data parameter. Doing so, it assumes that the host
pointer size is always 64-bit, which breaks on 32-bit :
../tests/qtest/stm32l4x5_gpio-test.c: In function ‘test_gpio_output_mode’:
../tests/qtest/stm32l4x5_gpio-test.c:272:25: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
272 | unsigned int pin = ((uint64_t)data) & 0xF;
| ^
../tests/qtest/stm32l4x5_gpio-test.c:273:22: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
273 | uint32_t gpio = ((uint64_t)data) >> 32;
| ^
To fix, improve the mangling of the GPIO address and pin number fields
by using GPIO_SIZE so that the resulting value fits in a 32-bit pointer.
While at it, include some helpers to hide the details.
Cc: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Cc: Inès Varhol <ines.varhol@telecom-paris.fr>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Message-id: 20240329092747.298259-1-clg@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Cédric Le Goater
Peter Maydell
parent
44e25fbc19
commit
27c335a464
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@ -76,6 +76,17 @@ const uint32_t idr_reset[NUM_GPIOS] = {
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0x00000000
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};
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#define PIN_MASK 0xF
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#define GPIO_ADDR_MASK (~(GPIO_SIZE - 1))
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static inline void *test_data(uint32_t gpio_addr, uint8_t pin)
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{
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return (void *)(uintptr_t)((gpio_addr & GPIO_ADDR_MASK) | (pin & PIN_MASK));
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}
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#define test_gpio_addr(data) ((uintptr_t)(data) & GPIO_ADDR_MASK)
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#define test_pin(data) ((uintptr_t)(data) & PIN_MASK)
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static uint32_t gpio_readl(unsigned int gpio, unsigned int offset)
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{
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return readl(gpio + offset);
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@ -269,8 +280,8 @@ static void test_gpio_output_mode(const void *data)
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* Additionally, it checks that values written to ODR
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* when not in output mode are stored and not discarded.
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*/
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unsigned int pin = ((uint64_t)data) & 0xF;
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uint32_t gpio = ((uint64_t)data) >> 32;
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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unsigned int gpio_id = get_gpio_id(gpio);
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qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
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@ -304,8 +315,8 @@ static void test_gpio_input_mode(const void *data)
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* corresponding GPIO line high/low : it should set the
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* right bit in IDR and send an irq to syscfg.
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*/
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unsigned int pin = ((uint64_t)data) & 0xF;
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uint32_t gpio = ((uint64_t)data) >> 32;
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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unsigned int gpio_id = get_gpio_id(gpio);
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qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
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@ -333,8 +344,8 @@ static void test_pull_up_pull_down(const void *data)
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* Test that a floating pin with pull-up sets the pin
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* high and vice-versa.
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*/
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unsigned int pin = ((uint64_t)data) & 0xF;
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uint32_t gpio = ((uint64_t)data) >> 32;
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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unsigned int gpio_id = get_gpio_id(gpio);
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qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
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@ -363,8 +374,8 @@ static void test_push_pull(const void *data)
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* disconnects the pin, that the pin can't be set or reset
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* externally afterwards.
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*/
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unsigned int pin = ((uint64_t)data) & 0xF;
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uint32_t gpio = ((uint64_t)data) >> 32;
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
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qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
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@ -410,8 +421,8 @@ static void test_open_drain(const void *data)
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* However a pin set low externally shouldn't be disconnected,
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* and it can be set low externally when in open-drain mode.
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*/
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unsigned int pin = ((uint64_t)data) & 0xF;
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uint32_t gpio = ((uint64_t)data) >> 32;
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
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qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
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@ -466,8 +477,8 @@ static void test_bsrr_brr(const void *data)
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* has the desired effect on ODR.
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* In BSRR, BSx has priority over BRx.
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*/
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unsigned int pin = ((uint64_t)data) & 0xF;
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uint32_t gpio = ((uint64_t)data) >> 32;
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unsigned int pin = test_pin(data);
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uint32_t gpio = test_gpio_addr(data);
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gpio_writel(gpio, BSRR, (1 << pin));
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g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
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@ -507,40 +518,40 @@ int main(int argc, char **argv)
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* is problematic since the pin was already high.
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*/
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qtest_add_data_func("stm32l4x5/gpio/test_gpioc5_output_mode",
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(void *)((uint64_t)GPIO_C << 32 | 5),
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test_data(GPIO_C, 5),
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test_gpio_output_mode);
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qtest_add_data_func("stm32l4x5/gpio/test_gpioh3_output_mode",
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(void *)((uint64_t)GPIO_H << 32 | 3),
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test_data(GPIO_H, 3),
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test_gpio_output_mode);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode1",
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(void *)((uint64_t)GPIO_D << 32 | 6),
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test_data(GPIO_D, 6),
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test_gpio_input_mode);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode2",
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(void *)((uint64_t)GPIO_C << 32 | 10),
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test_data(GPIO_C, 10),
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test_gpio_input_mode);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down1",
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(void *)((uint64_t)GPIO_B << 32 | 5),
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test_data(GPIO_B, 5),
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test_pull_up_pull_down);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down2",
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(void *)((uint64_t)GPIO_F << 32 | 1),
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test_data(GPIO_F, 1),
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test_pull_up_pull_down);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull1",
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(void *)((uint64_t)GPIO_G << 32 | 6),
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test_data(GPIO_G, 6),
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test_push_pull);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull2",
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(void *)((uint64_t)GPIO_H << 32 | 3),
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test_data(GPIO_H, 3),
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test_push_pull);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain1",
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(void *)((uint64_t)GPIO_C << 32 | 4),
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test_data(GPIO_C, 4),
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test_open_drain);
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qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain2",
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(void *)((uint64_t)GPIO_E << 32 | 11),
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test_data(GPIO_E, 11),
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test_open_drain);
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qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr1",
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(void *)((uint64_t)GPIO_A << 32 | 12),
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test_data(GPIO_A, 12),
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test_bsrr_brr);
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qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2",
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(void *)((uint64_t)GPIO_D << 32 | 0),
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test_data(GPIO_D, 0),
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test_bsrr_brr);
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qtest_start("-machine b-l475e-iot01a");
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